1/*
2 * Copyright (C) 2014-2016, Toradex AG
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7// Register Output for PF0100 programmer
8// Customer: Toradex AG
9// Program: Apalis iMX6
10// Sample marking:
11// Date: 12.02.2014
12// Time: 17:16:41
13// Generated from Spreadsheet Revision: P1.8
14
15/* sed commands to get from programmer script to struct */
16/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
17   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
18   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
19
20enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
21struct pmic_otp_prog_t{
22	unsigned char cmd;
23	unsigned char reg;
24	unsigned short value;
25};
26
27struct pmic_otp_prog_t pmic_otp_prog[] = {
28{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
29{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
30{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
31{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
32{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
33{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
34{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
35{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
36{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
37{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
38{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
39{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
40{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
41{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
42{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
43{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
44{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
45{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
46{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
47{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
48{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
49{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
50{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
51{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
52{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
53{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
54{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
55{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
56{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
57{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
58{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
59{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
60
61#if 0 /* TBB mode */
62{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
63{pmic_delay, 0, 10},
64#else
65// Write OTP
66{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
67{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
68{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
69{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
70{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
71{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
72{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
73{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
74//-----------------------------------------------------------------------------------
75{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
82{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
83{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
84{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
85//-----------------------------------------------------------------------------------
86{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
87//VPGM:DOWN:n
88//VPGM:UP:n
89{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
90//-----------------------------------------------------------------------------------
91// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
92//-----------------------------------------------------------------------------------
93// BANK 1
94//-----------------------------------------------------------------------------------
95{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
96{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
97{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
98{pmic_delay, 0, 10}, // Allow time for bank programming to complete
99{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
100{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
101//-----------------------------------------------------------------------------------
102// BANK 2
103//-----------------------------------------------------------------------------------
104{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
105{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
106{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
107{pmic_delay, 0, 10}, // Allow time for bank programming to complete
108{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
109{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
110//-----------------------------------------------------------------------------------
111// BANK 3
112//-----------------------------------------------------------------------------------
113{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
114{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
115{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
116{pmic_delay, 0, 10}, // Allow time for bank programming to complete
117{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
118{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
119//-----------------------------------------------------------------------------------
120// BANK 4
121//-----------------------------------------------------------------------------------
122{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
123{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
124{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
125{pmic_delay, 0, 10}, // Allow time for bank programming to complete
126{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
127{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
128//-----------------------------------------------------------------------------------
129// BANK 5
130//-----------------------------------------------------------------------------------
131{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
132{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
133{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
134{pmic_delay, 0, 10}, // Allow time for bank programming to complete
135{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
136{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
137//-----------------------------------------------------------------------------------
138// BANK 6
139//-----------------------------------------------------------------------------------
140{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
141{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
142{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
143{pmic_delay, 0, 10}, // Allow time for bank programming to complete
144{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
145{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
146//-----------------------------------------------------------------------------------
147// BANK 7
148//-----------------------------------------------------------------------------------
149{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
150{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
151{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
152{pmic_delay, 0, 10}, // Allow time for bank programming to complete
153{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
154{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
155//-----------------------------------------------------------------------------------
156// BANK 8
157//-----------------------------------------------------------------------------------
158{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
159{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
160{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
161{pmic_delay, 0, 10}, // Allow time for bank programming to complete
162{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
163{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
164//-----------------------------------------------------------------------------------
165// BANK 9
166//-----------------------------------------------------------------------------------
167{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
168{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
169{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
170{pmic_delay, 0, 10}, // Allow time for bank programming to complete
171{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
172{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
173//-----------------------------------------------------------------------------------
174// BANK 10
175//-----------------------------------------------------------------------------------
176{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
177{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
178{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
179{pmic_delay, 0, 10}, // Allow time for bank programming to complete
180{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
181{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
182//-----------------------------------------------------------------------------------
183{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
184{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
185{pmic_i2c, 0xD0, 0x00}, // Clear
186{pmic_i2c, 0xD1, 0x00}, // Clear
187{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
188{pmic_delay, 0, 500},
189{pmic_pwr, 0, 1},
190#endif
191};