1/* 2 * Copyright (C) 2013 Boundary Devices 3 * Copyright (C) 2014-2016, Toradex AG 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Device Configuration Data (DCD) 8 * 9 * Each entry must have the format: 10 * Addr-type Address Value 11 * 12 * where: 13 * Addr-type register length (1,2 or 4 bytes) 14 * Address absolute address of the register 15 * value value to be stored in the register 16 */ 17 18/* 19 * DDR3 settings 20 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), 21 * memory bus width: 64 bits x16/x32/x64 22 * MX6DL ddr is limited to 800 MHz(400 MHz clock) 23 * memory bus width: 64 bits x16/x32/x64 24 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) 25 * memory bus width: 32 bits x16/x32 26 */ 27DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 28DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 29DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 30DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 31DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 32DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 33DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 34DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 35 36DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 37DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 38DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 39DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 40DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 41DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 42DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 43DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 44DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 45/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 46DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 47 48DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 49DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 50DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 51DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 52DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 53DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 54DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 55DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 56 57DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 58DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 59DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 60DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 61 62DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 63DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 64DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 65 66DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 67DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 68 69/* (differential input) */ 70DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 71/* (differential input) */ 72DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 73/* disable ddr pullups */ 74DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 75DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 76/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 77DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 78 79/* Read data DQ Byte0-3 delay */ 80DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 81DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 82DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 83DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 84DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 85DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 86DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 87DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 88 89/* 90 * MDMISC mirroring interleaved (row/bank/col) 91 */ 92DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 93 94/* 95 * MDSCR con_req 96 */ 97DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 98