1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> 4 * Copyright (C) 2014-2016, Toradex AG 5 * copied from nitrogen6x 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/mxc_hdmi.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/iomux.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/mx6-pins.h> 18 #include <asm/arch/mx6-ddr.h> 19 #include <asm/bootm.h> 20 #include <asm/gpio.h> 21 #include <asm/io.h> 22 #include <asm/imx-common/iomux-v3.h> 23 #include <asm/imx-common/mxc_i2c.h> 24 #include <asm/imx-common/sata.h> 25 #include <asm/imx-common/boot_mode.h> 26 #include <asm/imx-common/video.h> 27 #include <dm/platform_data/serial_mxc.h> 28 #include <dm/platdata.h> 29 #include <fsl_esdhc.h> 30 #include <i2c.h> 31 #include <imx_thermal.h> 32 #include <linux/errno.h> 33 #include <malloc.h> 34 #include <mmc.h> 35 #include <micrel.h> 36 #include <miiphy.h> 37 #include <netdev.h> 38 39 #include "../common/tdx-cfg-block.h" 40 #ifdef CONFIG_TDX_CMD_IMX_MFGR 41 #include "pf0100.h" 42 #endif 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 48 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 49 50 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 51 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 52 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 53 54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 56 57 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 58 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 59 60 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 62 63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 65 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 66 67 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ 68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 69 PAD_CTL_SRE_SLOW) 70 71 #define NO_PULLUP ( \ 72 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 73 PAD_CTL_SRE_SLOW) 74 75 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 76 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 77 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 78 79 #define TRISTATE (PAD_CTL_HYS | PAD_CTL_SPEED_MED) 80 81 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 82 83 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST) 84 85 int dram_init(void) 86 { 87 /* use the DDR controllers configured size */ 88 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 89 (ulong)imx_ddr_size()); 90 91 return 0; 92 } 93 94 /* Apalis UART1 */ 95 iomux_v3_cfg_t const uart1_pads_dce[] = { 96 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 97 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 98 }; 99 iomux_v3_cfg_t const uart1_pads_dte[] = { 100 MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 101 MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 102 }; 103 104 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 105 /* Apalis I2C1 */ 106 struct i2c_pads_info i2c_pad_info1 = { 107 .scl = { 108 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, 109 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, 110 .gp = IMX_GPIO_NR(5, 27) 111 }, 112 .sda = { 113 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, 114 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, 115 .gp = IMX_GPIO_NR(5, 26) 116 } 117 }; 118 119 /* Apalis local, PMIC, SGTL5000, STMPE811 */ 120 struct i2c_pads_info i2c_pad_info_loc = { 121 .scl = { 122 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 123 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, 124 .gp = IMX_GPIO_NR(4, 12) 125 }, 126 .sda = { 127 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 128 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 129 .gp = IMX_GPIO_NR(4, 13) 130 } 131 }; 132 133 /* Apalis I2C3 / CAM */ 134 struct i2c_pads_info i2c_pad_info3 = { 135 .scl = { 136 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 137 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 138 .gp = IMX_GPIO_NR(3, 17) 139 }, 140 .sda = { 141 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 142 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 143 .gp = IMX_GPIO_NR(3, 18) 144 } 145 }; 146 147 /* Apalis I2C2 / DDC */ 148 struct i2c_pads_info i2c_pad_info_ddc = { 149 .scl = { 150 .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC, 151 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 152 .gp = IMX_GPIO_NR(2, 30) 153 }, 154 .sda = { 155 .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC, 156 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 157 .gp = IMX_GPIO_NR(3, 16) 158 } 159 }; 160 161 /* Apalis MMC1 */ 162 iomux_v3_cfg_t const usdhc1_pads[] = { 163 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 164 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 165 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 166 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 167 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 168 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 169 MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 170 MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 171 MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 172 MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 173 MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 174 # define GPIO_MMC_CD IMX_GPIO_NR(4, 20) 175 }; 176 177 /* Apalis SD1 */ 178 iomux_v3_cfg_t const usdhc2_pads[] = { 179 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 180 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 181 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 182 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 183 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 184 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 185 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 186 # define GPIO_SD_CD IMX_GPIO_NR(6, 14) 187 }; 188 189 /* eMMC */ 190 iomux_v3_cfg_t const usdhc3_pads[] = { 191 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 192 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 193 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 194 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 195 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 196 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 197 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 198 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 199 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 200 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 201 MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), 202 }; 203 204 int mx6_rgmii_rework(struct phy_device *phydev) 205 { 206 /* control data pad skew - devaddr = 0x02, register = 0x04 */ 207 ksz9031_phy_extended_write(phydev, 0x02, 208 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 209 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 210 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ 211 ksz9031_phy_extended_write(phydev, 0x02, 212 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 213 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 214 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ 215 ksz9031_phy_extended_write(phydev, 0x02, 216 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 217 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 218 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ 219 ksz9031_phy_extended_write(phydev, 0x02, 220 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 221 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); 222 return 0; 223 } 224 225 iomux_v3_cfg_t const enet_pads[] = { 226 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 227 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 228 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 229 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 230 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 231 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 232 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 233 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 234 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 235 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 236 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 237 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 238 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 239 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 240 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 241 /* KSZ9031 PHY Reset */ 242 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 243 # define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25) 244 }; 245 246 static void setup_iomux_enet(void) 247 { 248 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 249 } 250 251 static int reset_enet_phy(struct mii_dev *bus) 252 { 253 /* Reset KSZ9031 PHY */ 254 gpio_direction_output(GPIO_ENET_PHY_RESET, 0); 255 mdelay(10); 256 gpio_set_value(GPIO_ENET_PHY_RESET, 1); 257 258 return 0; 259 } 260 261 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */ 262 iomux_v3_cfg_t const gpio_pads[] = { 263 /* Apalis GPIO1 - GPIO8 */ 264 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), 265 MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), 266 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), 267 MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), 268 MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), 269 MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), 270 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLDOWN), 271 MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), 272 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), 273 }; 274 275 static void setup_iomux_gpio(void) 276 { 277 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); 278 } 279 280 iomux_v3_cfg_t const usb_pads[] = { 281 /* USBH_EN */ 282 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), 283 # define GPIO_USBH_EN IMX_GPIO_NR(1, 0) 284 /* USB_VBUS_DET */ 285 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 286 # define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28) 287 /* USBO1_ID */ 288 MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), 289 /* USBO1_EN */ 290 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 291 # define GPIO_USBO_EN IMX_GPIO_NR(3, 22) 292 }; 293 294 /* 295 * UARTs are used in DTE mode, switch the mode on all UARTs before 296 * any pinmuxing connects a (DCE) output to a transceiver output. 297 */ 298 #define UFCR 0x90 /* FIFO Control Register */ 299 #define UFCR_DCEDTE (1<<6) /* DCE=0 */ 300 301 static void setup_dtemode_uart(void) 302 { 303 setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); 304 setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); 305 setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE); 306 setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE); 307 } 308 static void setup_dcemode_uart(void) 309 { 310 clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE); 311 clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE); 312 clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE); 313 clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE); 314 } 315 316 static void setup_iomux_dte_uart(void) 317 { 318 setup_dtemode_uart(); 319 imx_iomux_v3_setup_multiple_pads(uart1_pads_dte, 320 ARRAY_SIZE(uart1_pads_dte)); 321 } 322 323 static void setup_iomux_dce_uart(void) 324 { 325 setup_dcemode_uart(); 326 imx_iomux_v3_setup_multiple_pads(uart1_pads_dce, 327 ARRAY_SIZE(uart1_pads_dce)); 328 } 329 330 #ifdef CONFIG_USB_EHCI_MX6 331 int board_ehci_hcd_init(int port) 332 { 333 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 334 return 0; 335 } 336 337 int board_ehci_power(int port, int on) 338 { 339 switch (port) { 340 case 0: 341 /* control OTG power */ 342 gpio_direction_output(GPIO_USBO_EN, on); 343 mdelay(100); 344 break; 345 case 1: 346 /* Control MXM USBH */ 347 gpio_direction_output(GPIO_USBH_EN, on); 348 mdelay(2); 349 /* Control onboard USB Hub VBUS */ 350 gpio_direction_output(GPIO_USB_VBUS_DET, on); 351 mdelay(100); 352 break; 353 default: 354 break; 355 } 356 return 0; 357 } 358 #endif 359 360 #ifdef CONFIG_FSL_ESDHC 361 /* use the following sequence: eMMC, MMC, SD */ 362 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { 363 {USDHC3_BASE_ADDR}, 364 {USDHC1_BASE_ADDR}, 365 {USDHC2_BASE_ADDR}, 366 }; 367 368 int board_mmc_getcd(struct mmc *mmc) 369 { 370 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 371 int ret = true; /* default: assume inserted */ 372 373 switch (cfg->esdhc_base) { 374 case USDHC1_BASE_ADDR: 375 gpio_direction_input(GPIO_MMC_CD); 376 ret = !gpio_get_value(GPIO_MMC_CD); 377 break; 378 case USDHC2_BASE_ADDR: 379 gpio_direction_input(GPIO_SD_CD); 380 ret = !gpio_get_value(GPIO_SD_CD); 381 break; 382 } 383 384 return ret; 385 } 386 387 int board_mmc_init(bd_t *bis) 388 { 389 #ifndef CONFIG_SPL_BUILD 390 s32 status = 0; 391 u32 index = 0; 392 393 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 394 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 395 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 396 397 usdhc_cfg[0].max_bus_width = 8; 398 usdhc_cfg[1].max_bus_width = 8; 399 usdhc_cfg[2].max_bus_width = 4; 400 401 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 402 switch (index) { 403 case 0: 404 imx_iomux_v3_setup_multiple_pads( 405 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 406 break; 407 case 1: 408 imx_iomux_v3_setup_multiple_pads( 409 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 410 break; 411 case 2: 412 imx_iomux_v3_setup_multiple_pads( 413 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 414 break; 415 default: 416 printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n", 417 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 418 return status; 419 } 420 421 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 422 } 423 424 return status; 425 #else 426 struct src *psrc = (struct src *)SRC_BASE_ADDR; 427 unsigned reg = readl(&psrc->sbmr1) >> 11; 428 /* 429 * Upon reading BOOT_CFG register the following map is done: 430 * Bit 11 and 12 of BOOT_CFG register can determine the current 431 * mmc port 432 * 0x1 SD1 433 * 0x2 SD2 434 * 0x3 SD4 435 */ 436 437 switch (reg & 0x3) { 438 case 0x0: 439 imx_iomux_v3_setup_multiple_pads( 440 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 441 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; 442 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 443 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 444 break; 445 case 0x1: 446 imx_iomux_v3_setup_multiple_pads( 447 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 448 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 449 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 450 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 451 break; 452 case 0x2: 453 imx_iomux_v3_setup_multiple_pads( 454 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 455 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; 456 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 457 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 458 break; 459 default: 460 puts("MMC boot device not available"); 461 } 462 463 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 464 #endif 465 } 466 #endif 467 468 int board_phy_config(struct phy_device *phydev) 469 { 470 mx6_rgmii_rework(phydev); 471 if (phydev->drv->config) 472 phydev->drv->config(phydev); 473 474 return 0; 475 } 476 477 int board_eth_init(bd_t *bis) 478 { 479 uint32_t base = IMX_FEC_BASE; 480 struct mii_dev *bus = NULL; 481 struct phy_device *phydev = NULL; 482 int ret; 483 484 setup_iomux_enet(); 485 486 #ifdef CONFIG_FEC_MXC 487 bus = fec_get_miibus(base, -1); 488 if (!bus) 489 return 0; 490 bus->reset = reset_enet_phy; 491 /* scan PHY 4,5,6,7 */ 492 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 493 if (!phydev) { 494 free(bus); 495 puts("no PHY found\n"); 496 return 0; 497 } 498 printf("using PHY at %d\n", phydev->addr); 499 ret = fec_probe(bis, -1, base, bus, phydev); 500 if (ret) { 501 printf("FEC MXC: %s:failed\n", __func__); 502 free(phydev); 503 free(bus); 504 } 505 #endif 506 return 0; 507 } 508 509 static iomux_v3_cfg_t const pwr_intb_pads[] = { 510 /* 511 * the bootrom sets the iomux to vselect, potentially connecting 512 * two outputs. Set this back to GPIO 513 */ 514 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) 515 }; 516 517 #if defined(CONFIG_VIDEO_IPUV3) 518 519 static iomux_v3_cfg_t const backlight_pads[] = { 520 /* Backlight on RGB connector: J15 */ 521 MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), 522 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13) 523 /* additional CPU pin on BKL_PWM, keep in tristate */ 524 MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE), 525 /* Backlight PWM, used as GPIO in U-Boot */ 526 MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 527 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10) 528 /* buffer output enable 0: buffer enabled */ 529 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), 530 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2) 531 /* PSAVE# integrated VDAC */ 532 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), 533 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31) 534 }; 535 536 static iomux_v3_cfg_t const rgb_pads[] = { 537 MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB), 538 MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB), 539 MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB), 540 MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB), 541 MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB), 542 MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB), 543 MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB), 544 MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB), 545 MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB), 546 MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB), 547 MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB), 548 MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB), 549 MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB), 550 MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB), 551 MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB), 552 MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB), 553 MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB), 554 MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB), 555 MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB), 556 MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB), 557 MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB), 558 MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB), 559 MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB), 560 MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB), 561 MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB), 562 MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB), 563 MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB), 564 MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB), 565 }; 566 567 static void do_enable_hdmi(struct display_info_t const *dev) 568 { 569 imx_enable_hdmi_phy(); 570 } 571 572 static int detect_i2c(struct display_info_t const *dev) 573 { 574 return (0 == i2c_set_bus_num(dev->bus)) && 575 (0 == i2c_probe(dev->addr)); 576 } 577 578 static void enable_lvds(struct display_info_t const *dev) 579 { 580 struct iomuxc *iomux = (struct iomuxc *) 581 IOMUXC_BASE_ADDR; 582 u32 reg = readl(&iomux->gpr[2]); 583 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 584 writel(reg, &iomux->gpr[2]); 585 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 586 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); 587 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); 588 } 589 590 static void enable_rgb(struct display_info_t const *dev) 591 { 592 imx_iomux_v3_setup_multiple_pads( 593 rgb_pads, 594 ARRAY_SIZE(rgb_pads)); 595 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 596 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); 597 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); 598 } 599 600 static int detect_default(struct display_info_t const *dev) 601 { 602 (void) dev; 603 return 1; 604 } 605 606 struct display_info_t const displays[] = {{ 607 .bus = -1, 608 .addr = 0, 609 .pixfmt = IPU_PIX_FMT_RGB24, 610 .detect = detect_hdmi, 611 .enable = do_enable_hdmi, 612 .mode = { 613 .name = "HDMI", 614 .refresh = 60, 615 .xres = 1024, 616 .yres = 768, 617 .pixclock = 15385, 618 .left_margin = 220, 619 .right_margin = 40, 620 .upper_margin = 21, 621 .lower_margin = 7, 622 .hsync_len = 60, 623 .vsync_len = 10, 624 .sync = FB_SYNC_EXT, 625 .vmode = FB_VMODE_NONINTERLACED 626 } }, { 627 .bus = -1, 628 .addr = 0, 629 .di = 1, 630 .pixfmt = IPU_PIX_FMT_RGB24, 631 .detect = detect_default, 632 .enable = enable_rgb, 633 .mode = { 634 .name = "vga-rgb", 635 .refresh = 60, 636 .xres = 640, 637 .yres = 480, 638 .pixclock = 33000, 639 .left_margin = 48, 640 .right_margin = 16, 641 .upper_margin = 31, 642 .lower_margin = 11, 643 .hsync_len = 96, 644 .vsync_len = 2, 645 .sync = 0, 646 .vmode = FB_VMODE_NONINTERLACED 647 } }, { 648 .bus = -1, 649 .addr = 0, 650 .di = 1, 651 .pixfmt = IPU_PIX_FMT_RGB24, 652 .enable = enable_rgb, 653 .mode = { 654 .name = "wvga-rgb", 655 .refresh = 60, 656 .xres = 800, 657 .yres = 480, 658 .pixclock = 25000, 659 .left_margin = 40, 660 .right_margin = 88, 661 .upper_margin = 33, 662 .lower_margin = 10, 663 .hsync_len = 128, 664 .vsync_len = 2, 665 .sync = 0, 666 .vmode = FB_VMODE_NONINTERLACED 667 } }, { 668 .bus = -1, 669 .addr = 0, 670 .pixfmt = IPU_PIX_FMT_LVDS666, 671 .detect = detect_i2c, 672 .enable = enable_lvds, 673 .mode = { 674 .name = "wsvga-lvds", 675 .refresh = 60, 676 .xres = 1024, 677 .yres = 600, 678 .pixclock = 15385, 679 .left_margin = 220, 680 .right_margin = 40, 681 .upper_margin = 21, 682 .lower_margin = 7, 683 .hsync_len = 60, 684 .vsync_len = 10, 685 .sync = FB_SYNC_EXT, 686 .vmode = FB_VMODE_NONINTERLACED 687 } } }; 688 size_t display_count = ARRAY_SIZE(displays); 689 690 static void setup_display(void) 691 { 692 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 693 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 694 int reg; 695 696 enable_ipu_clock(); 697 imx_setup_hdmi(); 698 /* Turn on LDB0,IPU,IPU DI0 clocks */ 699 reg = __raw_readl(&mxc_ccm->CCGR3); 700 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 701 writel(reg, &mxc_ccm->CCGR3); 702 703 /* set LDB0, LDB1 clk select to 011/011 */ 704 reg = readl(&mxc_ccm->cs2cdr); 705 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 706 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 707 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 708 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 709 writel(reg, &mxc_ccm->cs2cdr); 710 711 reg = readl(&mxc_ccm->cscmr2); 712 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 713 writel(reg, &mxc_ccm->cscmr2); 714 715 reg = readl(&mxc_ccm->chsccdr); 716 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 717 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 718 writel(reg, &mxc_ccm->chsccdr); 719 720 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 721 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 722 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 723 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 724 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 725 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 726 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 727 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 728 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 729 writel(reg, &iomux->gpr[2]); 730 731 reg = readl(&iomux->gpr[3]); 732 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK 733 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 734 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 735 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 736 writel(reg, &iomux->gpr[3]); 737 738 /* backlight unconditionally on for now */ 739 imx_iomux_v3_setup_multiple_pads(backlight_pads, 740 ARRAY_SIZE(backlight_pads)); 741 /* use 0 for EDT 7", use 1 for LG fullHD panel */ 742 gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0); 743 gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0); 744 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 745 } 746 #endif /* defined(CONFIG_VIDEO_IPUV3) */ 747 748 int board_early_init_f(void) 749 { 750 imx_iomux_v3_setup_multiple_pads(pwr_intb_pads, 751 ARRAY_SIZE(pwr_intb_pads)); 752 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0 753 setup_iomux_dte_uart(); 754 #else 755 setup_iomux_dce_uart(); 756 #endif 757 758 #if defined(CONFIG_VIDEO_IPUV3) 759 setup_display(); 760 #endif 761 return 0; 762 } 763 764 /* 765 * Do not overwrite the console 766 * Use always serial for U-Boot console 767 */ 768 int overwrite_console(void) 769 { 770 return 1; 771 } 772 773 int board_init(void) 774 { 775 /* address of boot parameters */ 776 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 777 778 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 779 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); 780 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); 781 782 #ifdef CONFIG_TDX_CMD_IMX_MFGR 783 (void) pmic_init(); 784 #endif 785 786 #ifdef CONFIG_CMD_SATA 787 setup_sata(); 788 #endif 789 790 setup_iomux_gpio(); 791 792 return 0; 793 } 794 795 #ifdef CONFIG_BOARD_LATE_INIT 796 int board_late_init(void) 797 { 798 #if defined(CONFIG_REVISION_TAG) && \ 799 defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) 800 char env_str[256]; 801 u32 rev; 802 803 rev = get_board_rev(); 804 snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev); 805 setenv("board_rev", env_str); 806 807 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0 808 if ((rev & 0xfff0) == 0x0100) { 809 char *fdt_env; 810 811 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */ 812 setup_iomux_dce_uart(); 813 814 /* if using the default device tree, use version for V1.0 HW */ 815 fdt_env = getenv("fdt_file"); 816 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) { 817 setenv("fdt_file", FDT_FILE_V1_0); 818 printf("patching fdt_file to " FDT_FILE_V1_0 "\n"); 819 #ifndef CONFIG_ENV_IS_NOWHERE 820 saveenv(); 821 #endif 822 } 823 } 824 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */ 825 #endif /* CONFIG_REVISION_TAG */ 826 827 return 0; 828 } 829 #endif /* CONFIG_BOARD_LATE_INIT */ 830 831 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP) 832 int ft_system_setup(void *blob, bd_t *bd) 833 { 834 return 0; 835 } 836 #endif 837 838 int checkboard(void) 839 { 840 char it[] = " IT"; 841 int minc, maxc; 842 843 switch (get_cpu_temp_grade(&minc, &maxc)) { 844 case TEMP_AUTOMOTIVE: 845 case TEMP_INDUSTRIAL: 846 break; 847 case TEMP_EXTCOMMERCIAL: 848 default: 849 it[0] = 0; 850 }; 851 printf("Model: Toradex Apalis iMX6 %s %s%s\n", 852 is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad", 853 (gd->ram_size == 0x80000000) ? "2GB" : 854 (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it); 855 return 0; 856 } 857 858 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 859 int ft_board_setup(void *blob, bd_t *bd) 860 { 861 return ft_common_board_setup(blob, bd); 862 } 863 #endif 864 865 #ifdef CONFIG_CMD_BMODE 866 static const struct boot_mode board_boot_modes[] = { 867 /* 4-bit bus width */ 868 {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 869 {"sd", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 870 {NULL, 0}, 871 }; 872 #endif 873 874 int misc_init_r(void) 875 { 876 #ifdef CONFIG_CMD_BMODE 877 add_board_boot_modes(board_boot_modes); 878 #endif 879 return 0; 880 } 881 882 #ifdef CONFIG_LDO_BYPASS_CHECK 883 /* TODO, use external pmic, for now always ldo_enable */ 884 void ldo_mode_set(int ldo_bypass) 885 { 886 return; 887 } 888 #endif 889 890 #ifdef CONFIG_SPL_BUILD 891 #include <spl.h> 892 #include <libfdt.h> 893 #include "asm/arch/mx6q-ddr.h" 894 #include "asm/arch/iomux.h" 895 #include "asm/arch/crm_regs.h" 896 897 static int mx6_com_dcd_table[] = { 898 /* ddr-setup.cfg */ 899 MX6_IOM_DRAM_SDQS0, 0x00000030, 900 MX6_IOM_DRAM_SDQS1, 0x00000030, 901 MX6_IOM_DRAM_SDQS2, 0x00000030, 902 MX6_IOM_DRAM_SDQS3, 0x00000030, 903 MX6_IOM_DRAM_SDQS4, 0x00000030, 904 MX6_IOM_DRAM_SDQS5, 0x00000030, 905 MX6_IOM_DRAM_SDQS6, 0x00000030, 906 MX6_IOM_DRAM_SDQS7, 0x00000030, 907 908 MX6_IOM_GRP_B0DS, 0x00000030, 909 MX6_IOM_GRP_B1DS, 0x00000030, 910 MX6_IOM_GRP_B2DS, 0x00000030, 911 MX6_IOM_GRP_B3DS, 0x00000030, 912 MX6_IOM_GRP_B4DS, 0x00000030, 913 MX6_IOM_GRP_B5DS, 0x00000030, 914 MX6_IOM_GRP_B6DS, 0x00000030, 915 MX6_IOM_GRP_B7DS, 0x00000030, 916 MX6_IOM_GRP_ADDDS, 0x00000030, 917 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 918 MX6_IOM_GRP_CTLDS, 0x00000030, 919 920 MX6_IOM_DRAM_DQM0, 0x00020030, 921 MX6_IOM_DRAM_DQM1, 0x00020030, 922 MX6_IOM_DRAM_DQM2, 0x00020030, 923 MX6_IOM_DRAM_DQM3, 0x00020030, 924 MX6_IOM_DRAM_DQM4, 0x00020030, 925 MX6_IOM_DRAM_DQM5, 0x00020030, 926 MX6_IOM_DRAM_DQM6, 0x00020030, 927 MX6_IOM_DRAM_DQM7, 0x00020030, 928 929 MX6_IOM_DRAM_CAS, 0x00020030, 930 MX6_IOM_DRAM_RAS, 0x00020030, 931 MX6_IOM_DRAM_SDCLK_0, 0x00020030, 932 MX6_IOM_DRAM_SDCLK_1, 0x00020030, 933 934 MX6_IOM_DRAM_RESET, 0x00020030, 935 MX6_IOM_DRAM_SDCKE0, 0x00003000, 936 MX6_IOM_DRAM_SDCKE1, 0x00003000, 937 938 MX6_IOM_DRAM_SDODT0, 0x00003030, 939 MX6_IOM_DRAM_SDODT1, 0x00003030, 940 941 /* (differential input) */ 942 MX6_IOM_DDRMODE_CTL, 0x00020000, 943 /* (differential input) */ 944 MX6_IOM_GRP_DDRMODE, 0x00020000, 945 /* disable ddr pullups */ 946 MX6_IOM_GRP_DDRPKE, 0x00000000, 947 MX6_IOM_DRAM_SDBA2, 0x00000000, 948 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 949 MX6_IOM_GRP_DDR_TYPE, 0x000C0000, 950 951 /* Read data DQ Byte0-3 delay */ 952 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, 953 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, 954 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, 955 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, 956 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, 957 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, 958 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, 959 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, 960 961 /* 962 * MDMISC mirroring interleaved (row/bank/col) 963 */ 964 MX6_MMDC_P0_MDMISC, 0x00081740, 965 966 /* 967 * MDSCR con_req 968 */ 969 MX6_MMDC_P0_MDSCR, 0x00008000, 970 971 /* 1066mhz_4x128mx16.cfg */ 972 973 MX6_MMDC_P0_MDPDC, 0x00020036, 974 MX6_MMDC_P0_MDCFG0, 0x555A7954, 975 MX6_MMDC_P0_MDCFG1, 0xDB328F64, 976 MX6_MMDC_P0_MDCFG2, 0x01FF00DB, 977 MX6_MMDC_P0_MDRWD, 0x000026D2, 978 MX6_MMDC_P0_MDOR, 0x005A1023, 979 MX6_MMDC_P0_MDOTC, 0x09555050, 980 MX6_MMDC_P0_MDPDC, 0x00025576, 981 MX6_MMDC_P0_MDASP, 0x00000027, 982 MX6_MMDC_P0_MDCTL, 0x831A0000, 983 MX6_MMDC_P0_MDSCR, 0x04088032, 984 MX6_MMDC_P0_MDSCR, 0x00008033, 985 MX6_MMDC_P0_MDSCR, 0x00428031, 986 MX6_MMDC_P0_MDSCR, 0x19308030, 987 MX6_MMDC_P0_MDSCR, 0x04008040, 988 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, 989 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, 990 MX6_MMDC_P0_MDREF, 0x00005800, 991 MX6_MMDC_P0_MPODTCTRL, 0x00000000, 992 MX6_MMDC_P1_MPODTCTRL, 0x00000000, 993 994 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338, 995 MX6_MMDC_P0_MPDGCTRL1, 0x03260324, 996 MX6_MMDC_P1_MPDGCTRL0, 0x43340344, 997 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C, 998 999 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E, 1000 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37, 1001 1002 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C, 1003 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F, 1004 1005 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E, 1006 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B, 1007 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015, 1008 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E, 1009 1010 MX6_MMDC_P0_MPMUR0, 0x00000800, 1011 MX6_MMDC_P1_MPMUR0, 0x00000800, 1012 MX6_MMDC_P0_MDSCR, 0x00000000, 1013 MX6_MMDC_P0_MAPSR, 0x00011006, 1014 }; 1015 1016 static int mx6_it_dcd_table[] = { 1017 /* ddr-setup.cfg */ 1018 MX6_IOM_DRAM_SDQS0, 0x00000030, 1019 MX6_IOM_DRAM_SDQS1, 0x00000030, 1020 MX6_IOM_DRAM_SDQS2, 0x00000030, 1021 MX6_IOM_DRAM_SDQS3, 0x00000030, 1022 MX6_IOM_DRAM_SDQS4, 0x00000030, 1023 MX6_IOM_DRAM_SDQS5, 0x00000030, 1024 MX6_IOM_DRAM_SDQS6, 0x00000030, 1025 MX6_IOM_DRAM_SDQS7, 0x00000030, 1026 1027 MX6_IOM_GRP_B0DS, 0x00000030, 1028 MX6_IOM_GRP_B1DS, 0x00000030, 1029 MX6_IOM_GRP_B2DS, 0x00000030, 1030 MX6_IOM_GRP_B3DS, 0x00000030, 1031 MX6_IOM_GRP_B4DS, 0x00000030, 1032 MX6_IOM_GRP_B5DS, 0x00000030, 1033 MX6_IOM_GRP_B6DS, 0x00000030, 1034 MX6_IOM_GRP_B7DS, 0x00000030, 1035 MX6_IOM_GRP_ADDDS, 0x00000030, 1036 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 1037 MX6_IOM_GRP_CTLDS, 0x00000030, 1038 1039 MX6_IOM_DRAM_DQM0, 0x00020030, 1040 MX6_IOM_DRAM_DQM1, 0x00020030, 1041 MX6_IOM_DRAM_DQM2, 0x00020030, 1042 MX6_IOM_DRAM_DQM3, 0x00020030, 1043 MX6_IOM_DRAM_DQM4, 0x00020030, 1044 MX6_IOM_DRAM_DQM5, 0x00020030, 1045 MX6_IOM_DRAM_DQM6, 0x00020030, 1046 MX6_IOM_DRAM_DQM7, 0x00020030, 1047 1048 MX6_IOM_DRAM_CAS, 0x00020030, 1049 MX6_IOM_DRAM_RAS, 0x00020030, 1050 MX6_IOM_DRAM_SDCLK_0, 0x00020030, 1051 MX6_IOM_DRAM_SDCLK_1, 0x00020030, 1052 1053 MX6_IOM_DRAM_RESET, 0x00020030, 1054 MX6_IOM_DRAM_SDCKE0, 0x00003000, 1055 MX6_IOM_DRAM_SDCKE1, 0x00003000, 1056 1057 MX6_IOM_DRAM_SDODT0, 0x00003030, 1058 MX6_IOM_DRAM_SDODT1, 0x00003030, 1059 1060 /* (differential input) */ 1061 MX6_IOM_DDRMODE_CTL, 0x00020000, 1062 /* (differential input) */ 1063 MX6_IOM_GRP_DDRMODE, 0x00020000, 1064 /* disable ddr pullups */ 1065 MX6_IOM_GRP_DDRPKE, 0x00000000, 1066 MX6_IOM_DRAM_SDBA2, 0x00000000, 1067 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 1068 MX6_IOM_GRP_DDR_TYPE, 0x000C0000, 1069 1070 /* Read data DQ Byte0-3 delay */ 1071 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, 1072 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, 1073 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, 1074 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, 1075 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, 1076 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, 1077 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, 1078 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, 1079 1080 /* 1081 * MDMISC mirroring interleaved (row/bank/col) 1082 */ 1083 MX6_MMDC_P0_MDMISC, 0x00081740, 1084 1085 /* 1086 * MDSCR con_req 1087 */ 1088 MX6_MMDC_P0_MDSCR, 0x00008000, 1089 1090 /* 1066mhz_4x256mx16.cfg */ 1091 1092 MX6_MMDC_P0_MDPDC, 0x00020036, 1093 MX6_MMDC_P0_MDCFG0, 0x898E78f5, 1094 MX6_MMDC_P0_MDCFG1, 0xff328f64, 1095 MX6_MMDC_P0_MDCFG2, 0x01FF00DB, 1096 MX6_MMDC_P0_MDRWD, 0x000026D2, 1097 MX6_MMDC_P0_MDOR, 0x008E1023, 1098 MX6_MMDC_P0_MDOTC, 0x09444040, 1099 MX6_MMDC_P0_MDPDC, 0x00025576, 1100 MX6_MMDC_P0_MDASP, 0x00000047, 1101 MX6_MMDC_P0_MDCTL, 0x841A0000, 1102 MX6_MMDC_P0_MDSCR, 0x02888032, 1103 MX6_MMDC_P0_MDSCR, 0x00008033, 1104 MX6_MMDC_P0_MDSCR, 0x00048031, 1105 MX6_MMDC_P0_MDSCR, 0x19408030, 1106 MX6_MMDC_P0_MDSCR, 0x04008040, 1107 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, 1108 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, 1109 MX6_MMDC_P0_MDREF, 0x00007800, 1110 MX6_MMDC_P0_MPODTCTRL, 0x00022227, 1111 MX6_MMDC_P1_MPODTCTRL, 0x00022227, 1112 1113 MX6_MMDC_P0_MPDGCTRL0, 0x03300338, 1114 MX6_MMDC_P0_MPDGCTRL1, 0x03240324, 1115 MX6_MMDC_P1_MPDGCTRL0, 0x03440350, 1116 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308, 1117 1118 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E, 1119 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46, 1120 1121 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E, 1122 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46, 1123 1124 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E, 1125 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B, 1126 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015, 1127 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E, 1128 1129 MX6_MMDC_P0_MPMUR0, 0x00000800, 1130 MX6_MMDC_P1_MPMUR0, 0x00000800, 1131 MX6_MMDC_P0_MDSCR, 0x00000000, 1132 MX6_MMDC_P0_MAPSR, 0x00011006, 1133 }; 1134 1135 1136 static void ccgr_init(void) 1137 { 1138 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1139 1140 writel(0x00C03F3F, &ccm->CCGR0); 1141 writel(0x0030FC03, &ccm->CCGR1); 1142 writel(0x0FFFFFF3, &ccm->CCGR2); 1143 writel(0x3FF0300F, &ccm->CCGR3); 1144 writel(0x00FFF300, &ccm->CCGR4); 1145 writel(0x0F0000F3, &ccm->CCGR5); 1146 writel(0x000003FF, &ccm->CCGR6); 1147 1148 /* 1149 * Setup CCM_CCOSR register as follows: 1150 * 1151 * cko1_en = 1 --> CKO1 enabled 1152 * cko1_div = 111 --> divide by 8 1153 * cko1_sel = 1011 --> ahb_clk_root 1154 * 1155 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz 1156 */ 1157 writel(0x000000FB, &ccm->ccosr); 1158 } 1159 1160 static void gpr_init(void) 1161 { 1162 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 1163 1164 /* enable AXI cache for VDOA/VPU/IPU */ 1165 writel(0xF00000CF, &iomux->gpr[4]); 1166 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 1167 writel(0x007F007F, &iomux->gpr[6]); 1168 writel(0x007F007F, &iomux->gpr[7]); 1169 } 1170 1171 static void ddr_init(int *table, int size) 1172 { 1173 int i; 1174 1175 for (i = 0; i < size / 2 ; i++) 1176 writel(table[2 * i + 1], table[2 * i]); 1177 } 1178 1179 static void spl_dram_init(void) 1180 { 1181 int minc, maxc; 1182 1183 switch (get_cpu_temp_grade(&minc, &maxc)) { 1184 case TEMP_COMMERCIAL: 1185 case TEMP_EXTCOMMERCIAL: 1186 puts("Commercial temperature grade DDR3 timings.\n"); 1187 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table)); 1188 break; 1189 case TEMP_INDUSTRIAL: 1190 case TEMP_AUTOMOTIVE: 1191 default: 1192 puts("Industrial temperature grade DDR3 timings.\n"); 1193 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table)); 1194 break; 1195 }; 1196 udelay(100); 1197 } 1198 1199 void board_init_f(ulong dummy) 1200 { 1201 /* setup AIPS and disable watchdog */ 1202 arch_cpu_init(); 1203 1204 ccgr_init(); 1205 gpr_init(); 1206 1207 /* iomux and setup of i2c */ 1208 board_early_init_f(); 1209 1210 /* setup GP timer */ 1211 timer_init(); 1212 1213 /* UART clocks enabled and gd valid - init serial console */ 1214 preloader_console_init(); 1215 1216 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0 1217 /* Make sure we use dte mode */ 1218 setup_dtemode_uart(); 1219 #endif 1220 1221 /* DDR initialization */ 1222 spl_dram_init(); 1223 1224 /* Clear the BSS. */ 1225 memset(__bss_start, 0, __bss_end - __bss_start); 1226 1227 /* load/boot image from boot device */ 1228 board_init_r(NULL, 0); 1229 } 1230 1231 void reset_cpu(ulong addr) 1232 { 1233 } 1234 1235 #endif 1236 1237 static struct mxc_serial_platdata mxc_serial_plat = { 1238 .reg = (struct mxc_uart *)UART1_BASE, 1239 .use_dte = true, 1240 }; 1241 1242 U_BOOT_DEVICE(mxc_serial) = { 1243 .name = "serial_mxc", 1244 .platdata = &mxc_serial_plat, 1245 }; 1246