1 /* 2 * Copyright (c) 2016 Toradex, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch-tegra/ap.h> 9 #include <asm/gpio.h> 10 #include <asm/io.h> 11 #include <asm/arch/gpio.h> 12 #include <asm/arch/pinmux.h> 13 #include <power/as3722.h> 14 15 #include "../common/tdx-common.h" 16 #include "pinmux-config-apalis-tk1.h" 17 18 #define LAN_RESET_N TEGRA_GPIO(S, 2) 19 20 int arch_misc_init(void) 21 { 22 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == 23 NVBOOTTYPE_RECOVERY) 24 printf("USB recovery mode\n"); 25 26 return 0; 27 } 28 29 int checkboard(void) 30 { 31 puts("Model: Toradex Apalis TK1 2GB\n"); 32 33 return 0; 34 } 35 36 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 37 int ft_board_setup(void *blob, bd_t *bd) 38 { 39 return ft_common_board_setup(blob, bd); 40 } 41 #endif 42 43 /* 44 * Routine: pinmux_init 45 * Description: Do individual peripheral pinmux configs 46 */ 47 void pinmux_init(void) 48 { 49 pinmux_clear_tristate_input_clamping(); 50 51 gpio_config_table(apalis_tk1_gpio_inits, 52 ARRAY_SIZE(apalis_tk1_gpio_inits)); 53 54 pinmux_config_pingrp_table(apalis_tk1_pingrps, 55 ARRAY_SIZE(apalis_tk1_pingrps)); 56 57 pinmux_config_drvgrp_table(apalis_tk1_drvgrps, 58 ARRAY_SIZE(apalis_tk1_drvgrps)); 59 } 60 61 #ifdef CONFIG_PCI_TEGRA 62 int tegra_pcie_board_init(void) 63 { 64 struct udevice *pmic; 65 int err; 66 67 err = as3722_init(&pmic); 68 if (err) { 69 error("failed to initialize AS3722 PMIC: %d\n", err); 70 return err; 71 } 72 73 err = as3722_sd_enable(pmic, 4); 74 if (err < 0) { 75 error("failed to enable SD4: %d\n", err); 76 return err; 77 } 78 79 err = as3722_sd_set_voltage(pmic, 4, 0x24); 80 if (err < 0) { 81 error("failed to set SD4 voltage: %d\n", err); 82 return err; 83 } 84 85 err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH | 86 AS3722_GPIO_INVERT); 87 if (err < 0) { 88 error("failed to configure GPIO#1 as output: %d\n", err); 89 return err; 90 } 91 92 err = as3722_gpio_direction_output(pmic, 2, 1); 93 if (err < 0) { 94 error("failed to set GPIO#2 high: %d\n", err); 95 return err; 96 } 97 98 /* Reset I210 Gigabit Ethernet Controller */ 99 gpio_request(LAN_RESET_N, "LAN_RESET_N"); 100 gpio_direction_output(LAN_RESET_N, 0); 101 102 /* 103 * Make sure we don't get any back feeding from LAN_WAKE_N resp. 104 * DEV_OFF_N 105 */ 106 gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N"); 107 gpio_direction_output(TEGRA_GPIO(O, 5), 0); 108 109 gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N"); 110 gpio_direction_output(TEGRA_GPIO(O, 6), 0); 111 112 /* Make sure LDO9 and LDO10 are initially enabled @ 0V */ 113 err = as3722_ldo_enable(pmic, 9); 114 if (err < 0) { 115 error("failed to enable LDO9: %d\n", err); 116 return err; 117 } 118 err = as3722_ldo_enable(pmic, 10); 119 if (err < 0) { 120 error("failed to enable LDO10: %d\n", err); 121 return err; 122 } 123 err = as3722_ldo_set_voltage(pmic, 9, 0x80); 124 if (err < 0) { 125 error("failed to set LDO9 voltage: %d\n", err); 126 return err; 127 } 128 err = as3722_ldo_set_voltage(pmic, 10, 0x80); 129 if (err < 0) { 130 error("failed to set LDO10 voltage: %d\n", err); 131 return err; 132 } 133 134 mdelay(100); 135 136 /* Make sure controller gets enabled by disabling DEV_OFF_N */ 137 gpio_set_value(TEGRA_GPIO(O, 6), 1); 138 139 /* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */ 140 err = as3722_ldo_set_voltage(pmic, 9, 0xff); 141 if (err < 0) { 142 error("failed to set LDO9 voltage: %d\n", err); 143 return err; 144 } 145 err = as3722_ldo_set_voltage(pmic, 10, 0xff); 146 if (err < 0) { 147 error("failed to set LDO10 voltage: %d\n", err); 148 return err; 149 } 150 151 mdelay(100); 152 gpio_set_value(LAN_RESET_N, 1); 153 154 #ifdef APALIS_TK1_PCIE_EVALBOARD_INIT 155 #define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */ 156 #define RESET_MOCI_CTRL TEGRA_GPIO(U, 4) 157 158 /* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation 159 Board */ 160 gpio_request(PEX_PERST_N, "PEX_PERST_N"); 161 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL"); 162 gpio_direction_output(PEX_PERST_N, 0); 163 gpio_direction_output(RESET_MOCI_CTRL, 0); 164 /* Must be asserted for 100 ms after power and clocks are stable */ 165 mdelay(100); 166 gpio_set_value(PEX_PERST_N, 1); 167 /* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until 168 900 us After PEX_PERST# De-assertion */ 169 mdelay(1); 170 gpio_set_value(RESET_MOCI_CTRL, 1); 171 #endif /* APALIS_T30_PCIE_EVALBOARD_INIT */ 172 173 return 0; 174 } 175 #endif /* CONFIG_PCI_TEGRA */ 176