10xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz) 20xf8000700 0x1202 // MIO configuration 30xf8000704 0x1202 40xf8000708 0x202 50xf800070c 0x202 60xf8000710 0x202 70xf8000714 0x202 80xf8000718 0x202 90xf800071c 0x200 100xf8000720 0x202 110xf8000724 0x202 120xf8000728 0x202 130xf800072c 0x202 140xf8000730 0x202 150xf8000734 0x202 160xf8000738 0x12e1 170xf800073c 0x12e0 180xf8000740 0x1202 190xf8000744 0x1202 200xf8000748 0x1202 210xf800074c 0x1202 220xf8000750 0x1202 230xf8000754 0x1202 240xf8000758 0x1203 250xf800075c 0x1203 260xf8000760 0x1203 270xf8000764 0x203 280xf8000768 0x1203 290xf800076c 0x203 300xf8000770 0x304 310xf8000774 0x305 320xf8000778 0x304 330xf800077c 0x305 340xf8000780 0x304 350xf8000784 0x304 360xf8000788 0x304 370xf800078c 0x304 380xf8000790 0x305 390xf8000794 0x304 400xf8000798 0x304 410xf800079c 0x304 420xf80007a0 0x380 430xf80007a4 0x380 440xf80007a8 0x380 450xf80007ac 0x380 460xf80007b0 0x380 470xf80007b4 0x380 480xf80007b8 0x1200 490xf80007bc 0x1201 500xf80007c0 0x1240 510xf80007c4 0x1240 520xf80007c8 0x1240 530xf80007cc 0x1240 540xf80007d0 0x1280 550xf80007d4 0x1280 560xf8000830 0x2f0037 570xf8000834 0x3a0039 580xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 590xE000D000 0x800238C1 // QSPI config - divide-by-2 600xE000D038 0x00000020 // QSPI loopback - internal, 0 delay 610xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash 62