1 /*
2  * (C) Copyright 2004-2008
3  * Texas Instruments, <www.ti.com>
4  *
5  * Author :
6  *	Sunil Kumar <sunilsaini05@gmail.com>
7  *	Shashi Ranjan <shashiranjanmca05@gmail.com>
8  *
9  * (C) Copyright 2009
10  * Frederik Kriewitz <frederik@kriewitz.eu>
11  *
12  * Derived from Beagle Board and 3430 SDP code by
13  *	Richard Woodruff <r-woodruff2@ti.com>
14  *	Syed Mohammed Khasim <khasim@ti.com>
15  *
16  *
17  * See file CREDITS for list of people who contributed to this
18  * project.
19  *
20  * This program is free software; you can redistribute it and/or
21  * modify it under the terms of the GNU General Public License as
22  * published by the Free Software Foundation; either version 2 of
23  * the License, or (at your option) any later version.
24  *
25  * This program is distributed in the hope that it will be useful,
26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28  * GNU General Public License for more details.
29  *
30  * You should have received a copy of the GNU General Public License
31  * along with this program; if not, write to the Free Software
32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33  * MA 02111-1307 USA
34  */
35 #include <common.h>
36 #include <twl4030.h>
37 #include <asm/io.h>
38 #include <asm/arch/mmc_host_def.h>
39 #include <asm/arch/mux.h>
40 #include <asm/arch/sys_proto.h>
41 #include <asm/arch/mem.h>
42 #include <asm/mach-types.h>
43 #include "devkit8000.h"
44 #ifdef CONFIG_DRIVER_DM9000
45 #include <net.h>
46 #include <netdev.h>
47 #endif
48 
49 DECLARE_GLOBAL_DATA_PTR;
50 
51 static u32 gpmc_net_config[GPMC_MAX_REG] = {
52 	NET_GPMC_CONFIG1,
53 	NET_GPMC_CONFIG2,
54 	NET_GPMC_CONFIG3,
55 	NET_GPMC_CONFIG4,
56 	NET_GPMC_CONFIG5,
57 	NET_GPMC_CONFIG6,
58 	0
59 };
60 
61 /*
62  * Routine: board_init
63  * Description: Early hardware init.
64  */
65 int board_init(void)
66 {
67 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
68 	/* board id for Linux */
69 	gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
70 	/* boot param addr */
71 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
72 
73 	return 0;
74 }
75 
76 /*
77  * Routine: misc_init_r
78  * Description: Configure board specific parts
79  */
80 int misc_init_r(void)
81 {
82 	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
83 #ifdef CONFIG_DRIVER_DM9000
84 	uchar enetaddr[6];
85 	u32 die_id_0;
86 #endif
87 
88 	twl4030_power_init();
89 #ifdef CONFIG_TWL4030_LED
90 	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
91 #endif
92 
93 #ifdef CONFIG_DRIVER_DM9000
94 	/* Configure GPMC registers for DM9000 */
95 	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
96 			CONFIG_DM9000_BASE, GPMC_SIZE_16M);
97 
98 	/* Use OMAP DIE_ID as MAC address */
99 	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
100 		printf("ethaddr not set, using Die ID\n");
101 		die_id_0 = readl(&id_base->die_id_0);
102 		enetaddr[0] = 0x02; /* locally administered */
103 		enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
104 		enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
105 		enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
106 		enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
107 		enetaddr[5] = (die_id_0 & 0x000000ff);
108 		eth_setenv_enetaddr("ethaddr", enetaddr);
109 	}
110 #endif
111 
112 	dieid_num_r();
113 
114 	return 0;
115 }
116 
117 /*
118  * Routine: set_muxconf_regs
119  * Description: Setting up the configuration Mux registers specific to the
120  *		hardware. Many pins need to be moved from protect to primary
121  *		mode.
122  */
123 void set_muxconf_regs(void)
124 {
125 	MUX_DEVKIT8000();
126 }
127 
128 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
129 int board_mmc_init(bd_t *bis)
130 {
131 	omap_mmc_init(0);
132 	return 0;
133 }
134 #endif
135 
136 #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
137 /*
138  * Routine: board_eth_init
139  * Description: Setting up the Ethernet hardware.
140  */
141 int board_eth_init(bd_t *bis)
142 {
143 	return dm9000_initialize(bis);
144 }
145 #endif
146 
147 /*
148  * Routine: get_board_mem_timings
149  * Description: If we use SPL then there is no x-loader nor config header
150  * so we have to setup the DDR timings ourself on the first bank.  This
151  * provides the timing values back to the function that configures
152  * the memory.  We have either one or two banks of 128MB DDR.
153  */
154 void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
155 		u32 *mr)
156 {
157 	/* General SDRC config */
158 	*mcfg = MICRON_V_MCFG_165(128 << 20);
159 	*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
160 
161 	/* AC timings */
162 	*ctrla = MICRON_V_ACTIMA_165;
163 	*ctrlb = MICRON_V_ACTIMB_165;
164 
165 	*mr = MICRON_V_MR_165;
166 }
167