1 /*
2  * Timll DevKit3250 board support, SPL board configuration
3  *
4  * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/emc.h>
14 #include <asm/arch-lpc32xx/gpio.h>
15 #include <spl.h>
16 
17 static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
18 
19 /*
20  * SDRAM K4S561632N-LC60 settings are selected in assumption that
21  * SDRAM clock may be set up to 166 MHz, however at the moment
22  * it is 104 MHz. Most delay values are converted to be a multiple of
23  * base clock, and precise pinned values are not needed here.
24  */
25 struct emc_dram_settings dram_64mb = {
26 	.cmddelay	= 0x0001C000,
27 	.config0	= 0x00005682,
28 	.rascas0	= 0x00000302,
29 	.rdconfig	= 0x00000011,	/* undocumented but crucial value */
30 
31 	.trp	= 83333333,
32 	.tras	= 23809524,
33 	.tsrex	= 12500000,
34 	.twr	= 83000000,		/* tWR = tRDL = 2 CLK */
35 	.trc	= 15384616,
36 	.trfc	= 15384616,
37 	.txsr	= 12500000,
38 	.trrd	= 1,
39 	.tmrd	= 1,
40 	.tcdlr	= 0,
41 
42 	.refresh	= 130000,	/* 800 clock cycles */
43 
44 	.mode	= 0x00018000,
45 	.emode	= 0x02000000,
46 };
47 
48 void spl_board_init(void)
49 {
50 	/* First of all silence buzzer controlled by GPO_20 */
51 	writel((1 << 20), &gpio->p3_outp_clr);
52 
53 	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
54 	preloader_console_init();
55 
56 	ddr_init(&dram_64mb);
57 
58 	/*
59 	 * NAND initialization is done by nand_init(),
60 	 * here just enable NAND SLC clocks
61 	 */
62 	lpc32xx_slc_nand_init();
63 }
64 
65 u32 spl_boot_device(void)
66 {
67 	return BOOT_DEVICE_NAND;
68 }
69