1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Timll DevKit3250 board support, SPL board configuration
4  *
5  * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
6  */
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/emc.h>
13 #include <asm/arch-lpc32xx/gpio.h>
14 #include <spl.h>
15 
16 static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
17 
18 /*
19  * SDRAM K4S561632N-LC60 settings are selected in assumption that
20  * SDRAM clock may be set up to 166 MHz, however at the moment
21  * it is 104 MHz. Most delay values are converted to be a multiple of
22  * base clock, and precise pinned values are not needed here.
23  */
24 struct emc_dram_settings dram_64mb = {
25 	.cmddelay	= 0x0001C000,
26 	.config0	= 0x00005682,
27 	.rascas0	= 0x00000302,
28 	.rdconfig	= 0x00000011,	/* undocumented but crucial value */
29 
30 	.trp	= 83333333,
31 	.tras	= 23809524,
32 	.tsrex	= 12500000,
33 	.twr	= 83000000,		/* tWR = tRDL = 2 CLK */
34 	.trc	= 15384616,
35 	.trfc	= 15384616,
36 	.txsr	= 12500000,
37 	.trrd	= 1,
38 	.tmrd	= 1,
39 	.tcdlr	= 0,
40 
41 	.refresh	= 130000,	/* 800 clock cycles */
42 
43 	.mode	= 0x00018000,
44 	.emode	= 0x02000000,
45 };
46 
47 void spl_board_init(void)
48 {
49 	/* First of all silence buzzer controlled by GPO_20 */
50 	writel((1 << 20), &gpio->p3_outp_clr);
51 
52 	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
53 	preloader_console_init();
54 
55 	ddr_init(&dram_64mb);
56 
57 	/*
58 	 * NAND initialization is done by nand_init(),
59 	 * here just enable NAND SLC clocks
60 	 */
61 	lpc32xx_slc_nand_init();
62 }
63 
64 u32 spl_boot_device(void)
65 {
66 	return BOOT_DEVICE_NAND;
67 }
68