1 /* 2 * evm.c 3 * 4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 5 * Antoine Tenart, <atenart@adeneo-embedded.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <spl.h> 12 #include <asm/cache.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/ddr_defs.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/mmc_host_def.h> 20 #include <asm/arch/mem.h> 21 #include <asm/arch/mux.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 int board_init(void) 26 { 27 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 28 return 0; 29 } 30 31 #ifdef CONFIG_SPL_BUILD 32 33 static struct module_pin_mux mmc_pin_mux[] = { 34 { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, 35 { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, 36 { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, 37 { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, 38 { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, 39 { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, 40 { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, 41 { -1 }, 42 }; 43 44 void set_uart_mux_conf(void) {} 45 46 void set_mux_conf_regs(void) 47 { 48 configure_module_pin_mux(mmc_pin_mux); 49 } 50 51 /* 52 * EMIF Paramters. Refer the EMIF register documentation and the 53 * memory datasheet for details. This is for 796 MHz. 54 */ 55 #define EMIF_TIM1 0x1779C9FE 56 #define EMIF_TIM2 0x50608074 57 #define EMIF_TIM3 0x009F857F 58 #define EMIF_SDREF 0x10001841 59 #define EMIF_SDCFG 0x62A73832 60 #define EMIF_PHYCFG 0x00000110 61 static const struct emif_regs ddr3_emif_regs = { 62 .sdram_config = EMIF_SDCFG, 63 .ref_ctrl = EMIF_SDREF, 64 .sdram_tim1 = EMIF_TIM1, 65 .sdram_tim2 = EMIF_TIM2, 66 .sdram_tim3 = EMIF_TIM3, 67 .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, 68 }; 69 70 static const struct cmd_control ddr3_ctrl = { 71 .cmd0csratio = 0x100, 72 .cmd0iclkout = 0x001, 73 .cmd1csratio = 0x100, 74 .cmd1iclkout = 0x001, 75 .cmd2csratio = 0x100, 76 .cmd2iclkout = 0x001, 77 }; 78 79 /* These values are obtained from the CCS app */ 80 #define RD_DQS_GATE (0x1B3) 81 #define RD_DQS (0x35) 82 #define WR_DQS (0x93) 83 static struct ddr_data ddr3_data = { 84 .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), 85 .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), 86 .datawiratio0 = ((0x20<<10) | 0x20<<0), 87 .datagiratio0 = ((0x20<<10) | 0x20<<0), 88 .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), 89 .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), 90 }; 91 92 static const struct dmm_lisa_map_regs evm_lisa_map_regs = { 93 .dmm_lisa_map_0 = 0x00000000, 94 .dmm_lisa_map_1 = 0x00000000, 95 .dmm_lisa_map_2 = 0x80640300, 96 .dmm_lisa_map_3 = 0xC0640320, 97 }; 98 99 void sdram_init(void) 100 { 101 /* 102 * Pass in our DDR3 config information and that we have 2 EMIFs to 103 * configure. 104 */ 105 config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs, 106 &evm_lisa_map_regs, 2); 107 } 108 #endif /* CONFIG_SPL_BUILD */ 109