1 /* 2 * evm.c 3 * 4 * Board functions for TI814x EVM 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <common.h> 20 #include <cpsw.h> 21 #include <errno.h> 22 #include <spl.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/omap.h> 26 #include <asm/arch/ddr_defs.h> 27 #include <asm/arch/clock.h> 28 #include <asm/arch/gpio.h> 29 #include <asm/arch/mmc_host_def.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/io.h> 32 #include <asm/emif.h> 33 #include <asm/gpio.h> 34 #include "evm.h" 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifdef CONFIG_SPL_BUILD 39 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 40 #endif 41 42 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 43 44 /* UART Defines */ 45 #ifdef CONFIG_SPL_BUILD 46 static void uart_enable(void) 47 { 48 /* UART softreset */ 49 uart_soft_reset(); 50 } 51 52 static void wdt_disable(void) 53 { 54 writel(0xAAAA, &wdtimer->wdtwspr); 55 while (readl(&wdtimer->wdtwwps) != 0x0) 56 ; 57 writel(0x5555, &wdtimer->wdtwspr); 58 while (readl(&wdtimer->wdtwwps) != 0x0) 59 ; 60 } 61 62 static const struct cmd_control evm_ddr2_cctrl_data = { 63 .cmd0csratio = 0x80, 64 .cmd0dldiff = 0x04, 65 .cmd0iclkout = 0x00, 66 67 .cmd1csratio = 0x80, 68 .cmd1dldiff = 0x04, 69 .cmd1iclkout = 0x00, 70 71 .cmd2csratio = 0x80, 72 .cmd2dldiff = 0x04, 73 .cmd2iclkout = 0x00, 74 }; 75 76 static const struct emif_regs evm_ddr2_emif0_regs = { 77 .sdram_config = 0x40801ab2, 78 .ref_ctrl = 0x10000c30, 79 .sdram_tim1 = 0x0aaaf552, 80 .sdram_tim2 = 0x043631d2, 81 .sdram_tim3 = 0x00000327, 82 .emif_ddr_phy_ctlr_1 = 0x00000007 83 }; 84 85 static const struct emif_regs evm_ddr2_emif1_regs = { 86 .sdram_config = 0x40801ab2, 87 .ref_ctrl = 0x10000c30, 88 .sdram_tim1 = 0x0aaaf552, 89 .sdram_tim2 = 0x043631d2, 90 .sdram_tim3 = 0x00000327, 91 .emif_ddr_phy_ctlr_1 = 0x00000007 92 }; 93 94 const struct dmm_lisa_map_regs evm_lisa_map_regs = { 95 .dmm_lisa_map_0 = 0x00000000, 96 .dmm_lisa_map_1 = 0x00000000, 97 .dmm_lisa_map_2 = 0x806c0300, 98 .dmm_lisa_map_3 = 0x806c0300, 99 }; 100 101 static const struct ddr_data evm_ddr2_data = { 102 .datardsratio0 = ((0x35<<10) | (0x35<<0)), 103 .datawdsratio0 = ((0x20<<10) | (0x20<<0)), 104 .datawiratio0 = ((0<<10) | (0<<0)), 105 .datagiratio0 = ((0<<10) | (0<<0)), 106 .datafwsratio0 = ((0x90<<10) | (0x90<<0)), 107 .datawrsratio0 = ((0x50<<10) | (0x50<<0)), 108 .datauserank0delay = 1, 109 .datadldiff0 = 0x4, 110 }; 111 #endif 112 113 /* 114 * early system init of muxing and clocks. 115 */ 116 void s_init(void) 117 { 118 #ifdef CONFIG_SPL_BUILD 119 /* 120 * Save the boot parameters passed from romcode. 121 * We cannot delay the saving further than this, 122 * to prevent overwrites. 123 */ 124 #ifdef CONFIG_SPL_BUILD 125 save_omap_boot_params(); 126 #endif 127 128 /* WDT1 is already running when the bootloader gets control 129 * Disable it to avoid "random" resets 130 */ 131 wdt_disable(); 132 133 /* Enable timer */ 134 timer_init(); 135 136 /* Setup the PLLs and the clocks for the peripherals */ 137 pll_init(); 138 139 /* Enable RTC32K clock */ 140 rtc32k_enable(); 141 142 /* Set UART pins */ 143 enable_uart0_pin_mux(); 144 145 /* Set MMC pins */ 146 enable_mmc1_pin_mux(); 147 148 /* Set Ethernet pins */ 149 enable_enet_pin_mux(); 150 151 /* Enable UART */ 152 uart_enable(); 153 154 gd = &gdata; 155 156 preloader_console_init(); 157 158 config_dmm(&evm_lisa_map_regs); 159 160 config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, 161 &evm_ddr2_emif0_regs, 0); 162 config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, 163 &evm_ddr2_emif1_regs, 1); 164 #endif 165 } 166 167 /* 168 * Basic board specific setup. Pinmux has been handled already. 169 */ 170 int board_init(void) 171 { 172 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 173 return 0; 174 } 175 176 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 177 int board_mmc_init(bd_t *bis) 178 { 179 omap_mmc_init(1, 0, 0, -1, -1); 180 181 return 0; 182 } 183 #endif 184 185 #ifdef CONFIG_DRIVER_TI_CPSW 186 static void cpsw_control(int enabled) 187 { 188 /* VTP can be added here */ 189 190 return; 191 } 192 193 static struct cpsw_slave_data cpsw_slaves[] = { 194 { 195 .slave_reg_ofs = 0x50, 196 .sliver_reg_ofs = 0x700, 197 .phy_id = 1, 198 }, 199 { 200 .slave_reg_ofs = 0x90, 201 .sliver_reg_ofs = 0x740, 202 .phy_id = 0, 203 }, 204 }; 205 206 static struct cpsw_platform_data cpsw_data = { 207 .mdio_base = CPSW_MDIO_BASE, 208 .cpsw_base = CPSW_BASE, 209 .mdio_div = 0xff, 210 .channels = 8, 211 .cpdma_reg_ofs = 0x100, 212 .slaves = 1, 213 .slave_data = cpsw_slaves, 214 .ale_reg_ofs = 0x600, 215 .ale_entries = 1024, 216 .host_port_reg_ofs = 0x28, 217 .hw_stats_reg_ofs = 0x400, 218 .mac_control = (1 << 5), 219 .control = cpsw_control, 220 .host_port_num = 0, 221 .version = CPSW_CTRL_VERSION_1, 222 }; 223 #endif 224 225 int board_eth_init(bd_t *bis) 226 { 227 uint8_t mac_addr[6]; 228 uint32_t mac_hi, mac_lo; 229 230 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 231 printf("<ethaddr> not set. Reading from E-fuse\n"); 232 /* try reading mac address from efuse */ 233 mac_lo = readl(&cdev->macid0l); 234 mac_hi = readl(&cdev->macid0h); 235 mac_addr[0] = mac_hi & 0xFF; 236 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 237 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 238 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 239 mac_addr[4] = mac_lo & 0xFF; 240 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 241 242 if (is_valid_ether_addr(mac_addr)) 243 eth_setenv_enetaddr("ethaddr", mac_addr); 244 else 245 printf("Unable to read MAC address. Set <ethaddr>\n"); 246 } 247 248 return cpsw_register(&cpsw_data); 249 } 250