1 /*
2  * (C) Copyright 2010
3  * Texas Instruments Incorporated, <www.ti.com>
4  *
5  *	Balaji Krishnamoorthy	<balajitk@ti.com>
6  *	Aneesh V		<aneesh@ti.com>
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 #ifndef _SDP4430_MUX_DATA_H
27 #define _SDP4430_MUX_DATA_H
28 
29 #include <asm/arch/mux_omap4.h>
30 
31 const struct pad_conf_entry core_padconf_array_non_essential[] = {
32 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
33 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
34 	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
35 	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
36 	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
37 	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
38 	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
39 	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
40 	{GPMC_A16, (M3)},						/* gpio_40 */
41 	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
42 	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
43 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
44 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
45 	{GPMC_A21, (M3)},						/* gpio_45 */
46 	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
47 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
48 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
49 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
50 	{GPMC_NCS0, (M3)},						/* gpio_50 */
51 	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
52 	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
53 	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
54 	{GPMC_NWP, (M3)},						/* gpio_54 */
55 	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
56 	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
57 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
58 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
59 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
60 	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
61 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
62 	{C2C_DATA12, (M1)},						/* dsi1_te0 */
63 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
64 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
65 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
66 	{HDMI_HPD, (M0)},						/* hdmi_hpd */
67 	{HDMI_CEC, (M0)},						/* hdmi_cec */
68 	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
69 	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
70 	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
71 	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
72 	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
73 	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
74 	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
75 	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
76 	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
77 	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
78 	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
79 	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
80 	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
81 	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
82 	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
83 	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
84 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
85 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
86 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
87 	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
88 	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
89 	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
90 	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
91 	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
92 	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
93 	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
94 	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
95 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
96 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
97 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
98 	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
99 	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
100 	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
101 	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
102 	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
103 	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
104 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
105 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
106 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
107 	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
108 	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
109 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
110 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
111 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
112 	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
113 	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
114 	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
115 	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
116 	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
117 	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
118 	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
119 	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
120 	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
121 	{UART2_RTS, (M0)},						/* uart2_rts */
122 	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
123 	{UART2_TX, (M0)},						/* uart2_tx */
124 	{HDQ_SIO, (M3)},						/* gpio_127 */
125 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
126 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
127 	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
128 	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
129 	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
130 	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
131 	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
132 	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
133 	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
134 	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
135 	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
136 	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
137 	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
138 	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
139 	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
140 	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
141 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
142 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
143 	{UART4_TX, (M0)},						/* uart4_tx */
144 	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
145 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
146 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
147 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
148 	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
149 	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
150 	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
151 	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
152 	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
153 	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
154 	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
155 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
156 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
157 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
158 	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
159 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
160 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
161 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
162 	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
163 	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
164 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
165 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
166 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
167 	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
168 	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
169 	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
170 	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
171 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
172 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
173 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
174 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
175 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
176 	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
177 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
178 	{SYS_BOOT1, (M3)},						/* gpio_185 */
179 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
180 	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
181 	{SYS_BOOT4, (M3)},						/* gpio_188 */
182 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
183 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
184 	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
185 	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
186 	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
187 	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
188 	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
189 	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
190 	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
191 	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
192 	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
193 	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
194 	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
195 	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
196 	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
197 	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
198 	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
199 	{DPM_EMU16, (M3)},						/* gpio_27 */
200 	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
201 	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
202 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
203 };
204 
205 const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
206 	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
207 	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
208 	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
209 	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
210 	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
211 	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
212 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
213 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
214 	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
215 	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
216 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
217 	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
218 	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
219 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
220 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
221 	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
222 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
223 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
224 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
225 	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
226 	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
227 	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
228 };
229 
230 #endif /* _SDP4430_MUX_DATA_H */
231