1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Balaji Krishnamoorthy <balajitk@ti.com> 6 * Aneesh V <aneesh@ti.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 #ifndef _PANDA_MUX_DATA_H_ 11 #define _PANDA_MUX_DATA_H_ 12 13 #include <asm/arch/mux_omap4.h> 14 15 16 const struct pad_conf_entry core_padconf_array_essential[] = { 17 18 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ 19 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ 20 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ 21 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ 22 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ 23 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ 24 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ 25 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ 26 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ 27 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ 28 {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ 29 {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ 30 {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ 31 {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ 32 {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ 33 {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ 34 {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ 35 {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ 36 {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ 37 {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ 38 {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ 39 {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ 40 {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ 41 {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ 42 {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ 43 {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ 44 {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ 45 {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ 46 {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ 47 {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ 48 {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ 49 {UART3_TX_IRTX, (M0)}, /* uart3_tx */ 50 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ 51 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ 52 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ 53 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ 54 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ 55 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ 56 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ 57 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ 58 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ 59 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ 60 {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ 61 {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ 62 {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ 63 {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ 64 {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ 65 {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ 66 {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ 67 {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ 68 {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ 69 70 }; 71 72 const struct pad_conf_entry wkup_padconf_array_essential[] = { 73 74 {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ 75 {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ 76 {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ 77 {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ 78 79 }; 80 81 const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { 82 83 {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ 84 85 }; 86 87 const struct pad_conf_entry core_padconf_array_non_essential[] = { 88 {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ 89 {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ 90 {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ 91 {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ 92 {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ 93 {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ 94 {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ 95 {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ 96 {GPMC_A16, (M3)}, /* gpio_40 */ 97 {GPMC_A17, (PTD | M3)}, /* gpio_41 */ 98 {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ 99 {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ 100 {GPMC_A20, (IEN | M3)}, /* gpio_44 */ 101 {GPMC_A21, (M3)}, /* gpio_45 */ 102 {GPMC_A22, (M3)}, /* gpio_46 */ 103 {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ 104 {GPMC_A24, (PTD | M3)}, /* gpio_48 */ 105 {GPMC_A25, (PTD | M3)}, /* gpio_49 */ 106 {GPMC_NCS0, (M3)}, /* gpio_50 */ 107 {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ 108 {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ 109 {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ 110 {GPMC_NWP, (M3)}, /* gpio_54 */ 111 {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ 112 {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ 113 {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ 114 {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ 115 {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ 116 {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ 117 {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ 118 {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ 119 {C2C_DATA14, (M1)}, /* dsi2_te0 */ 120 {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ 121 {HDMI_HPD, (M0)}, /* hdmi_hpd */ 122 {HDMI_CEC, (M0)}, /* hdmi_cec */ 123 {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ 124 {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ 125 {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ 126 {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ 127 {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ 128 {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ 129 {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ 130 {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ 131 {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ 132 {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ 133 {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ 134 {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ 135 {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ 136 {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ 137 {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ 138 {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ 139 {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ 140 {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ 141 {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ 142 {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ 143 {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ 144 {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ 145 {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ 146 {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ 147 {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ 148 {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ 149 {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ 150 {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ 151 {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ 152 {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ 153 {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ 154 {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ 155 {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ 156 {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ 157 {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ 158 {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ 159 {UART2_RTS, (M7)}, /* uart2_rts */ 160 {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ 161 {UART2_TX, (M7)}, /* uart2_tx */ 162 {HDQ_SIO, (M3)}, /* gpio_127 */ 163 {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ 164 {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ 165 {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ 166 {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ 167 {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ 168 {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ 169 {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ 170 {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ 171 {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ 172 {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ 173 {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ 174 {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ 175 {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ 176 {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ 177 {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ 178 {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ 179 {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ 180 {UART4_RX, (IEN | M0)}, /* uart4_rx */ 181 {UART4_TX, (M0)}, /* uart4_tx */ 182 {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ 183 {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ 184 {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ 185 {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ 186 {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ 187 {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ 188 {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ 189 {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ 190 {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ 191 {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ 192 {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ 193 {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ 194 {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ 195 {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ 196 {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ 197 {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ 198 {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ 199 {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ 200 {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ 201 {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ 202 {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ 203 {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ 204 {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ 205 {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ 206 {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ 207 {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ 208 {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ 209 {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ 210 {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ 211 {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ 212 {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ 213 {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ 214 {SYS_BOOT1, (M3)}, /* gpio_185 */ 215 {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ 216 {SYS_BOOT3, (M3)}, /* gpio_187 */ 217 {SYS_BOOT4, (M3)}, /* gpio_188 */ 218 {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ 219 {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ 220 {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ 221 {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ 222 {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ 223 {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ 224 {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ 225 {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ 226 {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ 227 {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ 228 {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ 229 {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ 230 {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ 231 {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ 232 {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ 233 {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ 234 {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ 235 {DPM_EMU16, (M3)}, /* gpio_27 */ 236 {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ 237 {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ 238 {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ 239 }; 240 241 const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { 242 {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ 243 }; 244 245 const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { 246 {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ 247 }; 248 249 const struct pad_conf_entry wkup_padconf_array_non_essential[] = { 250 {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ 251 {PAD1_SIM_CLK, (M0)}, /* sim_clk */ 252 {PAD0_SIM_RESET, (M0)}, /* sim_reset */ 253 {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ 254 {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ 255 {PAD1_FREF_XTAL_IN, (M0)}, /* # */ 256 {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ 257 {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ 258 {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ 259 {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ 260 {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ 261 {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ 262 {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ 263 {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ 264 {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ 265 {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ 266 {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ 267 }; 268 269 const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { 270 {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ 271 }; 272 273 #endif /* _PANDA_MUX_DATA_H_ */ 274