1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * Steve Sakoman <steve@sakoman.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 #include <common.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/arch/mmc_host_def.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/gpio.h> 14 15 #include "panda_mux_data.h" 16 17 #ifdef CONFIG_USB_EHCI 18 #include <usb.h> 19 #include <asm/arch/ehci.h> 20 #include <asm/ehci-omap.h> 21 #endif 22 23 #define PANDA_ULPI_PHY_TYPE_GPIO 182 24 #define PANDA_BOARD_ID_1_GPIO 101 25 #define PANDA_ES_BOARD_ID_1_GPIO 48 26 #define PANDA_BOARD_ID_2_GPIO 171 27 #define PANDA_ES_BOARD_ID_3_GPIO 3 28 #define PANDA_ES_BOARD_ID_4_GPIO 2 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 const struct omap_sysinfo sysinfo = { 33 "Board: OMAP4 Panda\n" 34 }; 35 36 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; 37 38 /** 39 * @brief board_init 40 * 41 * @return 0 42 */ 43 int board_init(void) 44 { 45 gpmc_init(); 46 47 gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA; 48 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 49 50 return 0; 51 } 52 53 int board_eth_init(bd_t *bis) 54 { 55 return 0; 56 } 57 58 /* 59 * Routine: get_board_revision 60 * Description: Detect if we are running on a panda revision A1-A6, 61 * or an ES panda board. This can be done by reading 62 * the level of GPIOs and checking the processor revisions. 63 * This should result in: 64 * Panda 4430: 65 * GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5 66 * GPIO171, GPIO101, GPIO182: 1 0 1 => A6 67 * Panda ES: 68 * GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2 69 * GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3 70 */ 71 int get_board_revision(void) 72 { 73 int board_id0, board_id1, board_id2; 74 int board_id3, board_id4; 75 int board_id; 76 77 int processor_rev = omap_revision(); 78 79 /* Setup the mux for the common board ID pins (gpio 171 and 182) */ 80 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); 81 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); 82 83 board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO); 84 board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO); 85 86 if ((processor_rev >= OMAP4460_ES1_0 && 87 processor_rev <= OMAP4460_ES1_1)) { 88 /* 89 * Setup the mux for the ES specific board ID pins (gpio 101, 90 * 2 and 3. 91 */ 92 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 93 GPMC_A24); 94 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 95 UNIPRO_RY0); 96 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 97 UNIPRO_RX1); 98 99 board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO); 100 board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO); 101 board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO); 102 103 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 104 setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es")); 105 #endif 106 board_id = ((board_id4 << 4) | (board_id3 << 3) | 107 (board_id2 << 2) | (board_id1 << 1) | (board_id0)); 108 } else { 109 /* Setup the mux for the Ax specific board ID pins (gpio 101) */ 110 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 111 FREF_CLK2_OUT); 112 113 board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO); 114 board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0)); 115 116 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 117 if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3)) 118 setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4")); 119 #endif 120 } 121 122 return board_id; 123 } 124 125 /** 126 * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES 127 * 128 * 129 * Detect if we are running on B3 version of ES panda board, 130 * This can be done by reading the level of GPIO 171 and checking the 131 * processor revisions. 132 * GPIO171: 1 => Panda ES Rev B3 133 * 134 * Return : return 1 if Panda ES Rev B3 , else return 0 135 */ 136 u8 is_panda_es_rev_b3(void) 137 { 138 int processor_rev = omap_revision(); 139 int ret = 0; 140 141 if ((processor_rev >= OMAP4460_ES1_0 && 142 processor_rev <= OMAP4460_ES1_1)) { 143 144 /* Setup the mux for the common board ID pins (gpio 171) */ 145 writew((IEN | M3), 146 (*ctrl)->control_padconf_core_base + UNIPRO_TX0); 147 148 /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */ 149 ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO); 150 } 151 return ret; 152 } 153 154 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 155 /* 156 * emif_get_reg_dump() - emif_get_reg_dump strong function 157 * 158 * @emif_nr - emif base 159 * @regs - reg dump of timing values 160 * 161 * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c 162 */ 163 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 164 { 165 u32 omap4_rev = omap_revision(); 166 167 /* Same devices and geometry on both EMIFs */ 168 if (omap4_rev == OMAP4430_ES1_0) 169 *regs = &emif_regs_elpida_380_mhz_1cs; 170 else if (omap4_rev == OMAP4430_ES2_0) 171 *regs = &emif_regs_elpida_200_mhz_2cs; 172 else if (omap4_rev == OMAP4430_ES2_3) 173 *regs = &emif_regs_elpida_400_mhz_1cs; 174 else if (omap4_rev < OMAP4470_ES1_0) { 175 if(is_panda_es_rev_b3()) 176 *regs = &emif_regs_elpida_400_mhz_1cs; 177 else 178 *regs = &emif_regs_elpida_400_mhz_2cs; 179 } 180 else 181 *regs = &emif_regs_elpida_400_mhz_1cs; 182 } 183 #endif 184 185 /** 186 * @brief misc_init_r - Configure Panda board specific configurations 187 * such as power configurations, ethernet initialization as phase2 of 188 * boot sequence 189 * 190 * @return 0 191 */ 192 int misc_init_r(void) 193 { 194 int phy_type; 195 u32 auxclk, altclksrc; 196 uint8_t device_mac[6]; 197 198 /* EHCI is not supported on ES1.0 */ 199 if (omap_revision() == OMAP4430_ES1_0) 200 return 0; 201 202 get_board_revision(); 203 204 gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO); 205 phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO); 206 207 if (phy_type == 1) { 208 /* ULPI PHY supplied by auxclk3 derived from sys_clk */ 209 debug("ULPI PHY supplied by auxclk3\n"); 210 211 auxclk = readl(&scrm->auxclk3); 212 /* Select sys_clk */ 213 auxclk &= ~AUXCLK_SRCSELECT_MASK; 214 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; 215 /* Set the divisor to 2 */ 216 auxclk &= ~AUXCLK_CLKDIV_MASK; 217 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; 218 /* Request auxilary clock #3 */ 219 auxclk |= AUXCLK_ENABLE_MASK; 220 221 writel(auxclk, &scrm->auxclk3); 222 } else { 223 /* ULPI PHY supplied by auxclk1 derived from PER dpll */ 224 debug("ULPI PHY supplied by auxclk1\n"); 225 226 auxclk = readl(&scrm->auxclk1); 227 /* Select per DPLL */ 228 auxclk &= ~AUXCLK_SRCSELECT_MASK; 229 auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT; 230 /* Set the divisor to 16 */ 231 auxclk &= ~AUXCLK_CLKDIV_MASK; 232 auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT; 233 /* Request auxilary clock #3 */ 234 auxclk |= AUXCLK_ENABLE_MASK; 235 236 writel(auxclk, &scrm->auxclk1); 237 } 238 239 altclksrc = readl(&scrm->altclksrc); 240 241 /* Activate alternate system clock supplier */ 242 altclksrc &= ~ALTCLKSRC_MODE_MASK; 243 altclksrc |= ALTCLKSRC_MODE_ACTIVE; 244 245 /* enable clocks */ 246 altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; 247 248 writel(altclksrc, &scrm->altclksrc); 249 250 if (!getenv("usbethaddr")) { 251 /* 252 * create a fake MAC address from the processor ID code. 253 * first byte is 0x02 to signify locally administered. 254 */ 255 device_mac[0] = 0x02; 256 device_mac[1] = readl(STD_FUSE_DIE_ID_3) & 0xff; 257 device_mac[2] = readl(STD_FUSE_DIE_ID_2) & 0xff; 258 device_mac[3] = readl(STD_FUSE_DIE_ID_1) & 0xff; 259 device_mac[4] = readl(STD_FUSE_DIE_ID_0) & 0xff; 260 device_mac[5] = (readl(STD_FUSE_DIE_ID_0) >> 8) & 0xff; 261 262 eth_setenv_enetaddr("usbethaddr", device_mac); 263 } 264 265 return 0; 266 } 267 268 void set_muxconf_regs_essential(void) 269 { 270 do_set_mux((*ctrl)->control_padconf_core_base, 271 core_padconf_array_essential, 272 sizeof(core_padconf_array_essential) / 273 sizeof(struct pad_conf_entry)); 274 275 do_set_mux((*ctrl)->control_padconf_wkup_base, 276 wkup_padconf_array_essential, 277 sizeof(wkup_padconf_array_essential) / 278 sizeof(struct pad_conf_entry)); 279 280 if (omap_revision() >= OMAP4460_ES1_0) 281 do_set_mux((*ctrl)->control_padconf_wkup_base, 282 wkup_padconf_array_essential_4460, 283 sizeof(wkup_padconf_array_essential_4460) / 284 sizeof(struct pad_conf_entry)); 285 } 286 287 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 288 int board_mmc_init(bd_t *bis) 289 { 290 return omap_mmc_init(0, 0, 0, -1, -1); 291 } 292 #endif 293 294 #ifdef CONFIG_USB_EHCI 295 296 static struct omap_usbhs_board_data usbhs_bdata = { 297 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 298 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, 299 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 300 }; 301 302 int ehci_hcd_init(int index, enum usb_init_type init, 303 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 304 { 305 int ret; 306 unsigned int utmi_clk; 307 308 /* Now we can enable our port clocks */ 309 utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); 310 utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; 311 sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk); 312 313 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 314 if (ret < 0) 315 return ret; 316 317 return 0; 318 } 319 320 int ehci_hcd_stop(int index) 321 { 322 return omap_ehci_hcd_stop(); 323 } 324 #endif 325 326 /* 327 * get_board_rev() - get board revision 328 */ 329 u32 get_board_rev(void) 330 { 331 return 0x20; 332 } 333