1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * Steve Sakoman <steve@sakoman.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 #include <common.h> 9 #include <asm/mach-types.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/mmc_host_def.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/gpio.h> 14 #include <asm/gpio.h> 15 #include <twl6030.h> 16 17 #include "panda_mux_data.h" 18 19 #ifdef CONFIG_USB_EHCI_HCD 20 #include <usb.h> 21 #include <asm/arch/ehci.h> 22 #include <asm/ehci-omap.h> 23 #endif 24 25 #define PANDA_ULPI_PHY_TYPE_GPIO 182 26 #define PANDA_BOARD_ID_1_GPIO 101 27 #define PANDA_ES_BOARD_ID_1_GPIO 48 28 #define PANDA_BOARD_ID_2_GPIO 171 29 #define PANDA_ES_BOARD_ID_3_GPIO 3 30 #define PANDA_ES_BOARD_ID_4_GPIO 2 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 const struct omap_sysinfo sysinfo = { 35 "Board: OMAP4 Panda\n" 36 }; 37 38 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; 39 40 /** 41 * @brief board_init 42 * 43 * @return 0 44 */ 45 int board_init(void) 46 { 47 gpmc_init(); 48 49 gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA; 50 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 51 52 return 0; 53 } 54 55 int board_eth_init(bd_t *bis) 56 { 57 return 0; 58 } 59 60 /* 61 * Routine: get_board_revision 62 * Description: Detect if we are running on a panda revision A1-A6, 63 * or an ES panda board. This can be done by reading 64 * the level of GPIOs and checking the processor revisions. 65 * This should result in: 66 * Panda 4430: 67 * GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5 68 * GPIO171, GPIO101, GPIO182: 1 0 1 => A6 69 * Panda ES: 70 * GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2 71 * GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3 72 */ 73 int get_board_revision(void) 74 { 75 int board_id0, board_id1, board_id2; 76 int board_id3, board_id4; 77 int board_id; 78 79 int processor_rev = omap_revision(); 80 81 /* Setup the mux for the common board ID pins (gpio 171 and 182) */ 82 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); 83 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); 84 85 board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO); 86 board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO); 87 88 if ((processor_rev >= OMAP4460_ES1_0 && 89 processor_rev <= OMAP4460_ES1_1)) { 90 /* 91 * Setup the mux for the ES specific board ID pins (gpio 101, 92 * 2 and 3. 93 */ 94 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 95 GPMC_A24); 96 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 97 UNIPRO_RY0); 98 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 99 UNIPRO_RX1); 100 101 board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO); 102 board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO); 103 board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO); 104 105 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 106 env_set("board_name", "panda-es"); 107 #endif 108 board_id = ((board_id4 << 4) | (board_id3 << 3) | 109 (board_id2 << 2) | (board_id1 << 1) | (board_id0)); 110 } else { 111 /* Setup the mux for the Ax specific board ID pins (gpio 101) */ 112 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 113 FREF_CLK2_OUT); 114 115 board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO); 116 board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0)); 117 118 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 119 if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3)) 120 env_set("board_name", "panda-a4"); 121 #endif 122 } 123 124 return board_id; 125 } 126 127 /** 128 * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES 129 * 130 * 131 * Detect if we are running on B3 version of ES panda board, 132 * This can be done by reading the level of GPIO 171 and checking the 133 * processor revisions. 134 * GPIO171: 1 => Panda ES Rev B3 135 * 136 * Return : return 1 if Panda ES Rev B3 , else return 0 137 */ 138 u8 is_panda_es_rev_b3(void) 139 { 140 int processor_rev = omap_revision(); 141 int ret = 0; 142 143 if ((processor_rev >= OMAP4460_ES1_0 && 144 processor_rev <= OMAP4460_ES1_1)) { 145 146 /* Setup the mux for the common board ID pins (gpio 171) */ 147 writew((IEN | M3), 148 (*ctrl)->control_padconf_core_base + UNIPRO_TX0); 149 150 /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */ 151 ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO); 152 } 153 return ret; 154 } 155 156 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 157 /* 158 * emif_get_reg_dump() - emif_get_reg_dump strong function 159 * 160 * @emif_nr - emif base 161 * @regs - reg dump of timing values 162 * 163 * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c 164 */ 165 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 166 { 167 u32 omap4_rev = omap_revision(); 168 169 /* Same devices and geometry on both EMIFs */ 170 if (omap4_rev == OMAP4430_ES1_0) 171 *regs = &emif_regs_elpida_380_mhz_1cs; 172 else if (omap4_rev == OMAP4430_ES2_0) 173 *regs = &emif_regs_elpida_200_mhz_2cs; 174 else if (omap4_rev == OMAP4430_ES2_3) 175 *regs = &emif_regs_elpida_400_mhz_1cs; 176 else if (omap4_rev < OMAP4470_ES1_0) { 177 if(is_panda_es_rev_b3()) 178 *regs = &emif_regs_elpida_400_mhz_1cs; 179 else 180 *regs = &emif_regs_elpida_400_mhz_2cs; 181 } 182 else 183 *regs = &emif_regs_elpida_400_mhz_1cs; 184 } 185 186 void emif_get_dmm_regs(const struct dmm_lisa_map_regs 187 **dmm_lisa_regs) 188 { 189 u32 omap_rev = omap_revision(); 190 191 if (omap_rev == OMAP4430_ES1_0) 192 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; 193 else if (omap_rev == OMAP4430_ES2_3) 194 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; 195 else if (omap_rev < OMAP4460_ES1_0) 196 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; 197 else 198 *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; 199 } 200 201 #endif 202 203 /** 204 * @brief misc_init_r - Configure Panda board specific configurations 205 * such as power configurations, ethernet initialization as phase2 of 206 * boot sequence 207 * 208 * @return 0 209 */ 210 int misc_init_r(void) 211 { 212 int phy_type; 213 u32 auxclk, altclksrc; 214 215 /* EHCI is not supported on ES1.0 */ 216 if (omap_revision() == OMAP4430_ES1_0) 217 return 0; 218 219 get_board_revision(); 220 221 gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO); 222 phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO); 223 224 if (phy_type == 1) { 225 /* ULPI PHY supplied by auxclk3 derived from sys_clk */ 226 debug("ULPI PHY supplied by auxclk3\n"); 227 228 auxclk = readl(&scrm->auxclk3); 229 /* Select sys_clk */ 230 auxclk &= ~AUXCLK_SRCSELECT_MASK; 231 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; 232 /* Set the divisor to 2 */ 233 auxclk &= ~AUXCLK_CLKDIV_MASK; 234 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; 235 /* Request auxilary clock #3 */ 236 auxclk |= AUXCLK_ENABLE_MASK; 237 238 writel(auxclk, &scrm->auxclk3); 239 } else { 240 /* ULPI PHY supplied by auxclk1 derived from PER dpll */ 241 debug("ULPI PHY supplied by auxclk1\n"); 242 243 auxclk = readl(&scrm->auxclk1); 244 /* Select per DPLL */ 245 auxclk &= ~AUXCLK_SRCSELECT_MASK; 246 auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT; 247 /* Set the divisor to 16 */ 248 auxclk &= ~AUXCLK_CLKDIV_MASK; 249 auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT; 250 /* Request auxilary clock #3 */ 251 auxclk |= AUXCLK_ENABLE_MASK; 252 253 writel(auxclk, &scrm->auxclk1); 254 } 255 256 altclksrc = readl(&scrm->altclksrc); 257 258 /* Activate alternate system clock supplier */ 259 altclksrc &= ~ALTCLKSRC_MODE_MASK; 260 altclksrc |= ALTCLKSRC_MODE_ACTIVE; 261 262 /* enable clocks */ 263 altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; 264 265 writel(altclksrc, &scrm->altclksrc); 266 267 omap_die_id_usbethaddr(); 268 269 return 0; 270 } 271 272 void set_muxconf_regs(void) 273 { 274 do_set_mux((*ctrl)->control_padconf_core_base, 275 core_padconf_array_essential, 276 sizeof(core_padconf_array_essential) / 277 sizeof(struct pad_conf_entry)); 278 279 do_set_mux((*ctrl)->control_padconf_wkup_base, 280 wkup_padconf_array_essential, 281 sizeof(wkup_padconf_array_essential) / 282 sizeof(struct pad_conf_entry)); 283 284 if (omap_revision() >= OMAP4460_ES1_0) 285 do_set_mux((*ctrl)->control_padconf_wkup_base, 286 wkup_padconf_array_essential_4460, 287 sizeof(wkup_padconf_array_essential_4460) / 288 sizeof(struct pad_conf_entry)); 289 } 290 291 #if defined(CONFIG_MMC) 292 int board_mmc_init(bd_t *bis) 293 { 294 return omap_mmc_init(0, 0, 0, -1, -1); 295 } 296 297 #if !defined(CONFIG_SPL_BUILD) 298 void board_mmc_power_init(void) 299 { 300 twl6030_power_mmc_init(0); 301 } 302 #endif 303 #endif 304 305 #ifdef CONFIG_USB_EHCI_HCD 306 307 static struct omap_usbhs_board_data usbhs_bdata = { 308 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 309 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, 310 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 311 }; 312 313 int ehci_hcd_init(int index, enum usb_init_type init, 314 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 315 { 316 int ret; 317 unsigned int utmi_clk; 318 319 /* Now we can enable our port clocks */ 320 utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); 321 utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; 322 setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk); 323 324 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 int ehci_hcd_stop(int index) 332 { 333 return omap_ehci_hcd_stop(); 334 } 335 #endif 336 337 /* 338 * get_board_rev() - get board revision 339 */ 340 u32 get_board_rev(void) 341 { 342 return 0x20; 343 } 344