1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * Steve Sakoman <steve@sakoman.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 #include <common.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/arch/mmc_host_def.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/gpio.h> 14 15 #include "panda_mux_data.h" 16 17 #ifdef CONFIG_USB_EHCI 18 #include <usb.h> 19 #include <asm/arch/ehci.h> 20 #include <asm/ehci-omap.h> 21 #endif 22 23 #define PANDA_ULPI_PHY_TYPE_GPIO 182 24 #define PANDA_BOARD_ID_1_GPIO 101 25 #define PANDA_ES_BOARD_ID_1_GPIO 48 26 #define PANDA_BOARD_ID_2_GPIO 171 27 #define PANDA_ES_BOARD_ID_3_GPIO 3 28 #define PANDA_ES_BOARD_ID_4_GPIO 2 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 const struct omap_sysinfo sysinfo = { 33 "Board: OMAP4 Panda\n" 34 }; 35 36 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; 37 38 /** 39 * @brief board_init 40 * 41 * @return 0 42 */ 43 int board_init(void) 44 { 45 gpmc_init(); 46 47 gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA; 48 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 49 50 return 0; 51 } 52 53 int board_eth_init(bd_t *bis) 54 { 55 return 0; 56 } 57 58 /* 59 * Routine: get_board_revision 60 * Description: Detect if we are running on a panda revision A1-A6, 61 * or an ES panda board. This can be done by reading 62 * the level of GPIOs and checking the processor revisions. 63 * This should result in: 64 * Panda 4430: 65 * GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5 66 * GPIO171, GPIO101, GPIO182: 1 0 1 => A6 67 * Panda ES: 68 * GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2 69 * GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3 70 */ 71 int get_board_revision(void) 72 { 73 int board_id0, board_id1, board_id2; 74 int board_id3, board_id4; 75 int board_id; 76 77 int processor_rev = omap_revision(); 78 79 /* Setup the mux for the common board ID pins (gpio 171 and 182) */ 80 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); 81 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); 82 83 board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO); 84 board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO); 85 86 if ((processor_rev >= OMAP4460_ES1_0 && 87 processor_rev <= OMAP4460_ES1_1)) { 88 /* 89 * Setup the mux for the ES specific board ID pins (gpio 101, 90 * 2 and 3. 91 */ 92 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 93 GPMC_A24); 94 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 95 UNIPRO_RY0); 96 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 97 UNIPRO_RX1); 98 99 board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO); 100 board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO); 101 board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO); 102 103 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 104 setenv("board_name", "panda-es"); 105 #endif 106 board_id = ((board_id4 << 4) | (board_id3 << 3) | 107 (board_id2 << 2) | (board_id1 << 1) | (board_id0)); 108 } else { 109 /* Setup the mux for the Ax specific board ID pins (gpio 101) */ 110 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 111 FREF_CLK2_OUT); 112 113 board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO); 114 board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0)); 115 116 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 117 if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3)) 118 setenv("board_name", "panda-a4"); 119 #endif 120 } 121 122 return board_id; 123 } 124 125 /** 126 * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES 127 * 128 * 129 * Detect if we are running on B3 version of ES panda board, 130 * This can be done by reading the level of GPIO 171 and checking the 131 * processor revisions. 132 * GPIO171: 1 => Panda ES Rev B3 133 * 134 * Return : return 1 if Panda ES Rev B3 , else return 0 135 */ 136 u8 is_panda_es_rev_b3(void) 137 { 138 int processor_rev = omap_revision(); 139 int ret = 0; 140 141 if ((processor_rev >= OMAP4460_ES1_0 && 142 processor_rev <= OMAP4460_ES1_1)) { 143 144 /* Setup the mux for the common board ID pins (gpio 171) */ 145 writew((IEN | M3), 146 (*ctrl)->control_padconf_core_base + UNIPRO_TX0); 147 148 /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */ 149 ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO); 150 } 151 return ret; 152 } 153 154 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 155 /* 156 * emif_get_reg_dump() - emif_get_reg_dump strong function 157 * 158 * @emif_nr - emif base 159 * @regs - reg dump of timing values 160 * 161 * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c 162 */ 163 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 164 { 165 u32 omap4_rev = omap_revision(); 166 167 /* Same devices and geometry on both EMIFs */ 168 if (omap4_rev == OMAP4430_ES1_0) 169 *regs = &emif_regs_elpida_380_mhz_1cs; 170 else if (omap4_rev == OMAP4430_ES2_0) 171 *regs = &emif_regs_elpida_200_mhz_2cs; 172 else if (omap4_rev == OMAP4430_ES2_3) 173 *regs = &emif_regs_elpida_400_mhz_1cs; 174 else if (omap4_rev < OMAP4470_ES1_0) { 175 if(is_panda_es_rev_b3()) 176 *regs = &emif_regs_elpida_400_mhz_1cs; 177 else 178 *regs = &emif_regs_elpida_400_mhz_2cs; 179 } 180 else 181 *regs = &emif_regs_elpida_400_mhz_1cs; 182 } 183 184 void emif_get_dmm_regs(const struct dmm_lisa_map_regs 185 **dmm_lisa_regs) 186 { 187 u32 omap_rev = omap_revision(); 188 189 if (omap_rev == OMAP4430_ES1_0) 190 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; 191 else if (omap_rev == OMAP4430_ES2_3) 192 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; 193 else if (omap_rev < OMAP4460_ES1_0) 194 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; 195 else 196 *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; 197 } 198 199 #endif 200 201 /** 202 * @brief misc_init_r - Configure Panda board specific configurations 203 * such as power configurations, ethernet initialization as phase2 of 204 * boot sequence 205 * 206 * @return 0 207 */ 208 int misc_init_r(void) 209 { 210 int phy_type; 211 u32 auxclk, altclksrc; 212 213 /* EHCI is not supported on ES1.0 */ 214 if (omap_revision() == OMAP4430_ES1_0) 215 return 0; 216 217 get_board_revision(); 218 219 gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO); 220 phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO); 221 222 if (phy_type == 1) { 223 /* ULPI PHY supplied by auxclk3 derived from sys_clk */ 224 debug("ULPI PHY supplied by auxclk3\n"); 225 226 auxclk = readl(&scrm->auxclk3); 227 /* Select sys_clk */ 228 auxclk &= ~AUXCLK_SRCSELECT_MASK; 229 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; 230 /* Set the divisor to 2 */ 231 auxclk &= ~AUXCLK_CLKDIV_MASK; 232 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; 233 /* Request auxilary clock #3 */ 234 auxclk |= AUXCLK_ENABLE_MASK; 235 236 writel(auxclk, &scrm->auxclk3); 237 } else { 238 /* ULPI PHY supplied by auxclk1 derived from PER dpll */ 239 debug("ULPI PHY supplied by auxclk1\n"); 240 241 auxclk = readl(&scrm->auxclk1); 242 /* Select per DPLL */ 243 auxclk &= ~AUXCLK_SRCSELECT_MASK; 244 auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT; 245 /* Set the divisor to 16 */ 246 auxclk &= ~AUXCLK_CLKDIV_MASK; 247 auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT; 248 /* Request auxilary clock #3 */ 249 auxclk |= AUXCLK_ENABLE_MASK; 250 251 writel(auxclk, &scrm->auxclk1); 252 } 253 254 altclksrc = readl(&scrm->altclksrc); 255 256 /* Activate alternate system clock supplier */ 257 altclksrc &= ~ALTCLKSRC_MODE_MASK; 258 altclksrc |= ALTCLKSRC_MODE_ACTIVE; 259 260 /* enable clocks */ 261 altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; 262 263 writel(altclksrc, &scrm->altclksrc); 264 265 omap_die_id_usbethaddr(); 266 267 return 0; 268 } 269 270 void set_muxconf_regs_essential(void) 271 { 272 do_set_mux((*ctrl)->control_padconf_core_base, 273 core_padconf_array_essential, 274 sizeof(core_padconf_array_essential) / 275 sizeof(struct pad_conf_entry)); 276 277 do_set_mux((*ctrl)->control_padconf_wkup_base, 278 wkup_padconf_array_essential, 279 sizeof(wkup_padconf_array_essential) / 280 sizeof(struct pad_conf_entry)); 281 282 if (omap_revision() >= OMAP4460_ES1_0) 283 do_set_mux((*ctrl)->control_padconf_wkup_base, 284 wkup_padconf_array_essential_4460, 285 sizeof(wkup_padconf_array_essential_4460) / 286 sizeof(struct pad_conf_entry)); 287 } 288 289 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 290 int board_mmc_init(bd_t *bis) 291 { 292 return omap_mmc_init(0, 0, 0, -1, -1); 293 } 294 #endif 295 296 #ifdef CONFIG_USB_EHCI 297 298 static struct omap_usbhs_board_data usbhs_bdata = { 299 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 300 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, 301 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 302 }; 303 304 int ehci_hcd_init(int index, enum usb_init_type init, 305 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 306 { 307 int ret; 308 unsigned int utmi_clk; 309 310 /* Now we can enable our port clocks */ 311 utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); 312 utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; 313 setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk); 314 315 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 int ehci_hcd_stop(int index) 323 { 324 return omap_ehci_hcd_stop(); 325 } 326 #endif 327 328 /* 329 * get_board_rev() - get board revision 330 */ 331 u32 get_board_rev(void) 332 { 333 return 0x20; 334 } 335