xref: /openbmc/u-boot/board/ti/panda/panda.c (revision 3f82d89d)
1 /*
2  * (C) Copyright 2010
3  * Texas Instruments Incorporated, <www.ti.com>
4  * Steve Sakoman  <steve@sakoman.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 #include <common.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/clocks.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/gpio.h>
30 
31 #include "panda_mux_data.h"
32 
33 #ifdef CONFIG_USB_EHCI
34 #include <usb.h>
35 #include <asm/arch/ehci.h>
36 #include <asm/ehci-omap.h>
37 #endif
38 
39 #define PANDA_ULPI_PHY_TYPE_GPIO       182
40 
41 DECLARE_GLOBAL_DATA_PTR;
42 
43 const struct omap_sysinfo sysinfo = {
44 	"Board: OMAP4 Panda\n"
45 };
46 
47 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
48 
49 /**
50  * @brief board_init
51  *
52  * @return 0
53  */
54 int board_init(void)
55 {
56 	gpmc_init();
57 
58 	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
59 	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
60 
61 	return 0;
62 }
63 
64 int board_eth_init(bd_t *bis)
65 {
66 	return 0;
67 }
68 
69 /**
70  * @brief misc_init_r - Configure Panda board specific configurations
71  * such as power configurations, ethernet initialization as phase2 of
72  * boot sequence
73  *
74  * @return 0
75  */
76 int misc_init_r(void)
77 {
78 	int phy_type;
79 	u32 auxclk, altclksrc;
80 
81 	/* EHCI is not supported on ES1.0 */
82 	if (omap_revision() == OMAP4430_ES1_0)
83 		return 0;
84 
85 	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
86 	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
87 
88 	if (phy_type == 1) {
89 		/* ULPI PHY supplied by auxclk3 derived from sys_clk */
90 		debug("ULPI PHY supplied by auxclk3\n");
91 
92 		auxclk = readl(&scrm->auxclk3);
93 		/* Select sys_clk */
94 		auxclk &= ~AUXCLK_SRCSELECT_MASK;
95 		auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
96 		/* Set the divisor to 2 */
97 		auxclk &= ~AUXCLK_CLKDIV_MASK;
98 		auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
99 		/* Request auxilary clock #3 */
100 		auxclk |= AUXCLK_ENABLE_MASK;
101 
102 		writel(auxclk, &scrm->auxclk3);
103        } else {
104 		/* ULPI PHY supplied by auxclk1 derived from PER dpll */
105 		debug("ULPI PHY supplied by auxclk1\n");
106 
107 		auxclk = readl(&scrm->auxclk1);
108 		/* Select per DPLL */
109 		auxclk &= ~AUXCLK_SRCSELECT_MASK;
110 		auxclk |=  AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
111 		/* Set the divisor to 16 */
112 		auxclk &= ~AUXCLK_CLKDIV_MASK;
113 		auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
114 		/* Request auxilary clock #3 */
115 		auxclk |= AUXCLK_ENABLE_MASK;
116 
117 		writel(auxclk, &scrm->auxclk1);
118 	}
119 
120 	altclksrc = readl(&scrm->altclksrc);
121 
122 	/* Activate alternate system clock supplier */
123 	altclksrc &= ~ALTCLKSRC_MODE_MASK;
124 	altclksrc |= ALTCLKSRC_MODE_ACTIVE;
125 
126 	/* enable clocks */
127 	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
128 
129 	writel(altclksrc, &scrm->altclksrc);
130 
131 	return 0;
132 }
133 
134 void set_muxconf_regs_essential(void)
135 {
136 	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
137 		   sizeof(core_padconf_array_essential) /
138 		   sizeof(struct pad_conf_entry));
139 
140 	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
141 		   sizeof(wkup_padconf_array_essential) /
142 		   sizeof(struct pad_conf_entry));
143 
144 	if (omap_revision() >= OMAP4460_ES1_0)
145 		do_set_mux(CONTROL_PADCONF_WKUP,
146 				 wkup_padconf_array_essential_4460,
147 				 sizeof(wkup_padconf_array_essential_4460) /
148 				 sizeof(struct pad_conf_entry));
149 }
150 
151 void set_muxconf_regs_non_essential(void)
152 {
153 	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
154 		   sizeof(core_padconf_array_non_essential) /
155 		   sizeof(struct pad_conf_entry));
156 
157 	if (omap_revision() < OMAP4460_ES1_0)
158 		do_set_mux(CONTROL_PADCONF_CORE,
159 				core_padconf_array_non_essential_4430,
160 				sizeof(core_padconf_array_non_essential_4430) /
161 				sizeof(struct pad_conf_entry));
162 	else
163 		do_set_mux(CONTROL_PADCONF_CORE,
164 				core_padconf_array_non_essential_4460,
165 				sizeof(core_padconf_array_non_essential_4460) /
166 				sizeof(struct pad_conf_entry));
167 
168 	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
169 		   sizeof(wkup_padconf_array_non_essential) /
170 		   sizeof(struct pad_conf_entry));
171 
172 	if (omap_revision() < OMAP4460_ES1_0)
173 		do_set_mux(CONTROL_PADCONF_WKUP,
174 				wkup_padconf_array_non_essential_4430,
175 				sizeof(wkup_padconf_array_non_essential_4430) /
176 				sizeof(struct pad_conf_entry));
177 }
178 
179 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
180 int board_mmc_init(bd_t *bis)
181 {
182 	omap_mmc_init(0, 0, 0);
183 	return 0;
184 }
185 #endif
186 
187 #ifdef CONFIG_USB_EHCI
188 
189 static struct omap_usbhs_board_data usbhs_bdata = {
190 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
191 	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
192 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
193 };
194 
195 int ehci_hcd_init(void)
196 {
197 	int ret;
198 	unsigned int utmi_clk;
199 
200 	/* Now we can enable our port clocks */
201 	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
202 	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
203 	sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
204 
205 	ret = omap_ehci_hcd_init(&usbhs_bdata);
206 	if (ret < 0)
207 		return ret;
208 
209 	return 0;
210 }
211 
212 int ehci_hcd_stop(void)
213 {
214 	return omap_ehci_hcd_stop();
215 }
216 #endif
217 
218 /*
219  * get_board_rev() - get board revision
220  */
221 u32 get_board_rev(void)
222 {
223 	return 0x20;
224 }
225