xref: /openbmc/u-boot/board/ti/panda/panda.c (revision 3bddafaa)
1 /*
2  * (C) Copyright 2010
3  * Texas Instruments Incorporated, <www.ti.com>
4  * Steve Sakoman  <steve@sakoman.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 #include <common.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/mmc_host_def.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/gpio.h>
14 
15 #include "panda_mux_data.h"
16 
17 #ifdef CONFIG_USB_EHCI
18 #include <usb.h>
19 #include <asm/arch/ehci.h>
20 #include <asm/ehci-omap.h>
21 #endif
22 
23 #define PANDA_ULPI_PHY_TYPE_GPIO       182
24 #define PANDA_BOARD_ID_1_GPIO          101
25 #define PANDA_ES_BOARD_ID_1_GPIO        48
26 #define PANDA_BOARD_ID_2_GPIO          171
27 #define PANDA_ES_BOARD_ID_3_GPIO         3
28 #define PANDA_ES_BOARD_ID_4_GPIO         2
29 
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 const struct omap_sysinfo sysinfo = {
33 	"Board: OMAP4 Panda\n"
34 };
35 
36 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
37 
38 /**
39  * @brief board_init
40  *
41  * @return 0
42  */
43 int board_init(void)
44 {
45 	gpmc_init();
46 
47 	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
48 	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
49 
50 	return 0;
51 }
52 
53 int board_eth_init(bd_t *bis)
54 {
55 	return 0;
56 }
57 
58 /*
59 * Routine: get_board_revision
60 * Description: Detect if we are running on a panda revision A1-A6,
61 *              or an ES panda board. This can be done by reading
62 *              the level of GPIOs and checking the processor revisions.
63 *              This should result in:
64 *			Panda 4430:
65 *              GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
66 *              GPIO171, GPIO101, GPIO182: 1 0 1 => A6
67 *			Panda ES:
68 *              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
69 *              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
70 */
71 int get_board_revision(void)
72 {
73 	int board_id0, board_id1, board_id2;
74 	int board_id3, board_id4;
75 	int board_id;
76 
77 	int processor_rev = omap_revision();
78 
79 	/* Setup the mux for the common board ID pins (gpio 171 and 182) */
80 	writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
81 	writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
82 
83 	board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
84 	board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
85 
86 	if ((processor_rev >= OMAP4460_ES1_0 &&
87 	     processor_rev <= OMAP4460_ES1_1)) {
88 		/*
89 		 * Setup the mux for the ES specific board ID pins (gpio 101,
90 		 * 2 and 3.
91 		 */
92 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
93 				GPMC_A24);
94 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
95 				UNIPRO_RY0);
96 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
97 				UNIPRO_RX1);
98 
99 		board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
100 		board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
101 		board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
102 
103 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
104 		setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
105 #endif
106 		board_id = ((board_id4 << 4) | (board_id3 << 3) |
107 			(board_id2 << 2) | (board_id1 << 1) | (board_id0));
108 	} else {
109 		/* Setup the mux for the Ax specific board ID pins (gpio 101) */
110 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
111 				FREF_CLK2_OUT);
112 
113 		board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
114 		board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
115 
116 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
117 		if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
118 			setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
119 #endif
120 	}
121 
122 	return board_id;
123 }
124 
125 /**
126  * @brief misc_init_r - Configure Panda board specific configurations
127  * such as power configurations, ethernet initialization as phase2 of
128  * boot sequence
129  *
130  * @return 0
131  */
132 int misc_init_r(void)
133 {
134 	int phy_type;
135 	u32 auxclk, altclksrc;
136 	uint8_t device_mac[6];
137 
138 	/* EHCI is not supported on ES1.0 */
139 	if (omap_revision() == OMAP4430_ES1_0)
140 		return 0;
141 
142 	get_board_revision();
143 
144 	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
145 	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
146 
147 	if (phy_type == 1) {
148 		/* ULPI PHY supplied by auxclk3 derived from sys_clk */
149 		debug("ULPI PHY supplied by auxclk3\n");
150 
151 		auxclk = readl(&scrm->auxclk3);
152 		/* Select sys_clk */
153 		auxclk &= ~AUXCLK_SRCSELECT_MASK;
154 		auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
155 		/* Set the divisor to 2 */
156 		auxclk &= ~AUXCLK_CLKDIV_MASK;
157 		auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
158 		/* Request auxilary clock #3 */
159 		auxclk |= AUXCLK_ENABLE_MASK;
160 
161 		writel(auxclk, &scrm->auxclk3);
162 	} else {
163 		/* ULPI PHY supplied by auxclk1 derived from PER dpll */
164 		debug("ULPI PHY supplied by auxclk1\n");
165 
166 		auxclk = readl(&scrm->auxclk1);
167 		/* Select per DPLL */
168 		auxclk &= ~AUXCLK_SRCSELECT_MASK;
169 		auxclk |=  AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
170 		/* Set the divisor to 16 */
171 		auxclk &= ~AUXCLK_CLKDIV_MASK;
172 		auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
173 		/* Request auxilary clock #3 */
174 		auxclk |= AUXCLK_ENABLE_MASK;
175 
176 		writel(auxclk, &scrm->auxclk1);
177 	}
178 
179 	altclksrc = readl(&scrm->altclksrc);
180 
181 	/* Activate alternate system clock supplier */
182 	altclksrc &= ~ALTCLKSRC_MODE_MASK;
183 	altclksrc |= ALTCLKSRC_MODE_ACTIVE;
184 
185 	/* enable clocks */
186 	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
187 
188 	writel(altclksrc, &scrm->altclksrc);
189 
190 	if (!getenv("usbethaddr")) {
191 		/*
192 		 * create a fake MAC address from the processor ID code.
193 		 * first byte is 0x02 to signify locally administered.
194 		 */
195 		device_mac[0] = 0x02;
196 		device_mac[1] = readl(STD_FUSE_DIE_ID_3) & 0xff;
197 		device_mac[2] = readl(STD_FUSE_DIE_ID_2) & 0xff;
198 		device_mac[3] = readl(STD_FUSE_DIE_ID_1) & 0xff;
199 		device_mac[4] = readl(STD_FUSE_DIE_ID_0) & 0xff;
200 		device_mac[5] = (readl(STD_FUSE_DIE_ID_0) >> 8) & 0xff;
201 
202 		eth_setenv_enetaddr("usbethaddr", device_mac);
203 	}
204 
205 	return 0;
206 }
207 
208 void set_muxconf_regs_essential(void)
209 {
210 	do_set_mux((*ctrl)->control_padconf_core_base,
211 		   core_padconf_array_essential,
212 		   sizeof(core_padconf_array_essential) /
213 		   sizeof(struct pad_conf_entry));
214 
215 	do_set_mux((*ctrl)->control_padconf_wkup_base,
216 		   wkup_padconf_array_essential,
217 		   sizeof(wkup_padconf_array_essential) /
218 		   sizeof(struct pad_conf_entry));
219 
220 	if (omap_revision() >= OMAP4460_ES1_0)
221 		do_set_mux((*ctrl)->control_padconf_wkup_base,
222 			   wkup_padconf_array_essential_4460,
223 			   sizeof(wkup_padconf_array_essential_4460) /
224 			   sizeof(struct pad_conf_entry));
225 }
226 
227 void set_muxconf_regs_non_essential(void)
228 {
229 	do_set_mux((*ctrl)->control_padconf_core_base,
230 		   core_padconf_array_non_essential,
231 		   sizeof(core_padconf_array_non_essential) /
232 		   sizeof(struct pad_conf_entry));
233 
234 	if (omap_revision() < OMAP4460_ES1_0)
235 		do_set_mux((*ctrl)->control_padconf_core_base,
236 			   core_padconf_array_non_essential_4430,
237 			   sizeof(core_padconf_array_non_essential_4430) /
238 			   sizeof(struct pad_conf_entry));
239 	else
240 		do_set_mux((*ctrl)->control_padconf_core_base,
241 			   core_padconf_array_non_essential_4460,
242 			   sizeof(core_padconf_array_non_essential_4460) /
243 			   sizeof(struct pad_conf_entry));
244 
245 	do_set_mux((*ctrl)->control_padconf_wkup_base,
246 		   wkup_padconf_array_non_essential,
247 		   sizeof(wkup_padconf_array_non_essential) /
248 		   sizeof(struct pad_conf_entry));
249 
250 	if (omap_revision() < OMAP4460_ES1_0)
251 		do_set_mux((*ctrl)->control_padconf_wkup_base,
252 			   wkup_padconf_array_non_essential_4430,
253 			   sizeof(wkup_padconf_array_non_essential_4430) /
254 			   sizeof(struct pad_conf_entry));
255 }
256 
257 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
258 int board_mmc_init(bd_t *bis)
259 {
260 	return omap_mmc_init(0, 0, 0, -1, -1);
261 }
262 #endif
263 
264 #ifdef CONFIG_USB_EHCI
265 
266 static struct omap_usbhs_board_data usbhs_bdata = {
267 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
268 	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
269 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
270 };
271 
272 int ehci_hcd_init(int index, enum usb_init_type init,
273 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
274 {
275 	int ret;
276 	unsigned int utmi_clk;
277 
278 	/* Now we can enable our port clocks */
279 	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
280 	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
281 	sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
282 
283 	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
284 	if (ret < 0)
285 		return ret;
286 
287 	return 0;
288 }
289 
290 int ehci_hcd_stop(int index)
291 {
292 	return omap_ehci_hcd_stop();
293 }
294 #endif
295 
296 /*
297  * get_board_rev() - get board revision
298  */
299 u32 get_board_rev(void)
300 {
301 	return 0x20;
302 }
303