1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Sricharan R <r.sricharan@ti.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 #ifndef _EVM5430_MUX_DATA_H 26 #define _EVM5430_MUX_DATA_H 27 28 #include <asm/arch/mux_omap5.h> 29 30 const struct pad_conf_entry core_padconf_array_essential[] = { 31 32 {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ 33 {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ 34 {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ 35 {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ 36 {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ 37 {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ 38 {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ 39 {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ 40 {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ 41 {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ 42 {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ 43 {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ 44 {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/ 45 {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/ 46 {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/ 47 {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ 48 {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ 49 {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ 50 {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ 51 {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ 52 {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ 53 {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ 54 {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ 55 {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ 56 {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ 57 {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ 58 {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ 59 60 }; 61 62 const struct pad_conf_entry wkup_padconf_array_essential[] = { 63 64 {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ 65 {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ 66 {SYS_32K, (IEN | M0)}, /* SYS_32K */ 67 68 }; 69 70 const struct pad_conf_entry core_padconf_array_non_essential[] = { 71 72 {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ 73 {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ 74 {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ 75 {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ 76 {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ 77 {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ 78 {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ 79 {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ 80 {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ 81 {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ 82 {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ 83 {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ 84 {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ 85 {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ 86 {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ 87 {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ 88 {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ 89 {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ 90 {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ 91 {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ 92 {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ 93 {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ 94 {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ 95 {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ 96 {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ 97 {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ 98 {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ 99 {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ 100 {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ 101 {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ 102 {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ 103 {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ 104 {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ 105 {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ 106 {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ 107 {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ 108 {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ 109 {HSI1_CADATA, (M6)}, /* GPIO3_71 */ 110 {UART1_TX, (M0)}, /* UART1_TX */ 111 {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ 112 {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ 113 {UART1_RTS, (M0)}, /* UART1_RTS */ 114 {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ 115 {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ 116 {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ 117 {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ 118 {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ 119 {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ 120 {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ 121 {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ 122 {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ 123 {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ 124 {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ 125 {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ 126 {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ 127 {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ 128 {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ 129 {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ 130 {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ 131 {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ 132 {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ 133 {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ 134 {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ 135 {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ 136 {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ 137 {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ 138 {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ 139 {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ 140 {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ 141 {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ 142 {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ 143 {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ 144 {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ 145 {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ 146 {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ 147 {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ 148 {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ 149 {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ 150 {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ 151 {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ 152 {RFBI_RE, (M4)}, /* KBD_COL4 */ 153 {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ 154 {RFBI_DATA8, (M4)}, /* KBD_COL3 */ 155 {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ 156 {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ 157 {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ 158 {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ 159 {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ 160 {RFBI_DATA14, (M4)}, /* KBD_COL7 */ 161 {RFBI_DATA15, (M4)}, /* KBD_COL6 */ 162 {GPIO6_182, (M6)}, /* GPIO6_182 */ 163 {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ 164 {GPIO6_184, (M4)}, /* KBD_COL2 */ 165 {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ 166 {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ 167 {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ 168 {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ 169 {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ 170 {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ 171 {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ 172 {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ 173 {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ 174 {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ 175 {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ 176 {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ 177 {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ 178 {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ 179 {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ 180 {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ 181 {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ 182 {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ 183 {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ 184 {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ 185 {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ 186 {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ 187 {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ 188 {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ 189 {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ 190 {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ 191 {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ 192 {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ 193 {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ 194 {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ 195 {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ 196 {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ 197 {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ 198 {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ 199 {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ 200 {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ 201 {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ 202 {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ 203 {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ 204 {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ 205 {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ 206 {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ 207 {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ 208 {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ 209 {CAM_STROBE, (M0)}, /* CAM_STROBE */ 210 {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ 211 {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ 212 {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ 213 {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ 214 {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ 215 {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ 216 {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ 217 {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ 218 {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ 219 {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ 220 {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ 221 {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ 222 {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ 223 {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ 224 {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ 225 {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ 226 {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ 227 {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ 228 {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ 229 {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ 230 {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ 231 {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ 232 {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ 233 {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ 234 {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ 235 {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ 236 {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ 237 {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ 238 {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ 239 {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ 240 {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ 241 {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ 242 {UART5_TX, (M0)}, /* UART5_TX */ 243 {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ 244 {UART5_RTS, (M0)}, /* UART5_RTS */ 245 {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ 246 {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ 247 {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ 248 {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ 249 {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ 250 {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ 251 {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ 252 {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ 253 {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ 254 {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ 255 {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ 256 {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ 257 {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ 258 {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ 259 {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ 260 {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ 261 {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ 262 {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ 263 {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ 264 265 }; 266 267 const struct pad_conf_entry wkup_padconf_array_non_essential[] = { 268 269 /* 270 * This pad keeps C2C Module always enabled. 271 * Putting this in safe mode do not cause the issue. 272 * C2C driver could enable this mux setting if needed. 273 */ 274 {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ 275 {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ 276 {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ 277 {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ 278 {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ 279 {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ 280 {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ 281 {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ 282 {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ 283 {JTAG_TDO, (M0)}, /* JTAG_TDO */ 284 {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ 285 {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ 286 {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ 287 {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ 288 {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ 289 {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ 290 {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ 291 {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ 292 {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ 293 {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ 294 {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ 295 {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ 296 {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ 297 {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ 298 {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ 299 {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ 300 {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ 301 302 }; 303 304 #endif /* _EVM4430_MUX_DATA_H */ 305