1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Sricharan R <r.sricharan@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #ifndef _EVM5430_MUX_DATA_H 10 #define _EVM5430_MUX_DATA_H 11 12 #include <asm/arch/mux_omap5.h> 13 14 const struct pad_conf_entry core_padconf_array_essential[] = { 15 16 {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ 17 {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ 18 {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ 19 {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ 20 {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ 21 {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ 22 {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ 23 {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ 24 {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ 25 {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ 26 {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ 27 {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ 28 {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/ 29 {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/ 30 {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/ 31 {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ 32 {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ 33 {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ 34 {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ 35 {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ 36 {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ 37 {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ 38 {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ 39 {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ 40 {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ 41 {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ 42 {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ 43 {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ 44 {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ 45 {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */ 46 {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */ 47 }; 48 49 const struct pad_conf_entry wkup_padconf_array_essential[] = { 50 51 {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ 52 {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ 53 {SYS_32K, (IEN | M0)}, /* SYS_32K */ 54 {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ 55 56 }; 57 58 const struct pad_conf_entry core_padconf_array_non_essential[] = { 59 60 {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ 61 {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ 62 {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ 63 {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ 64 {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ 65 {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ 66 {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ 67 {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ 68 {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ 69 {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ 70 {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ 71 {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ 72 {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ 73 {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ 74 {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ 75 {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ 76 {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ 77 {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ 78 {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ 79 {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ 80 {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ 81 {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ 82 {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ 83 {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ 84 {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ 85 {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ 86 {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ 87 {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ 88 {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ 89 {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ 90 {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ 91 {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ 92 {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ 93 {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ 94 {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ 95 {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ 96 {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ 97 {HSI1_CADATA, (M6)}, /* GPIO3_71 */ 98 {UART1_TX, (M0)}, /* UART1_TX */ 99 {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ 100 {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ 101 {UART1_RTS, (M0)}, /* UART1_RTS */ 102 {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ 103 {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ 104 {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ 105 {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ 106 {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ 107 {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ 108 {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ 109 {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ 110 {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ 111 {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ 112 {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ 113 {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ 114 {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ 115 {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ 116 {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ 117 {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ 118 {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ 119 {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ 120 {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ 121 {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ 122 {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ 123 {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ 124 {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ 125 {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ 126 {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ 127 {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ 128 {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ 129 {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ 130 {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ 131 {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ 132 {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ 133 {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ 134 {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ 135 {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ 136 {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ 137 {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ 138 {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ 139 {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ 140 {RFBI_RE, (M4)}, /* KBD_COL4 */ 141 {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ 142 {RFBI_DATA8, (M4)}, /* KBD_COL3 */ 143 {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ 144 {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ 145 {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ 146 {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ 147 {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ 148 {RFBI_DATA14, (M4)}, /* KBD_COL7 */ 149 {RFBI_DATA15, (M4)}, /* KBD_COL6 */ 150 {GPIO6_182, (M6)}, /* GPIO6_182 */ 151 {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ 152 {GPIO6_184, (M4)}, /* KBD_COL2 */ 153 {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ 154 {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ 155 {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ 156 {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ 157 {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ 158 {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ 159 {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ 160 {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ 161 {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ 162 {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ 163 {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ 164 {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ 165 {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ 166 {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ 167 {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ 168 {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ 169 {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ 170 {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ 171 {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ 172 {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ 173 {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ 174 {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ 175 {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ 176 {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ 177 {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ 178 {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ 179 {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ 180 {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ 181 {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ 182 {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ 183 {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ 184 {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ 185 {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ 186 {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ 187 {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ 188 {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ 189 {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ 190 {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ 191 {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ 192 {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ 193 {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ 194 {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ 195 {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ 196 {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ 197 {CAM_STROBE, (M0)}, /* CAM_STROBE */ 198 {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ 199 {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ 200 {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ 201 {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ 202 {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ 203 {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ 204 {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ 205 {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ 206 {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ 207 {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ 208 {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ 209 {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ 210 {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ 211 {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ 212 {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ 213 {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ 214 {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ 215 {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ 216 {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ 217 {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ 218 {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ 219 {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ 220 {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ 221 {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ 222 {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ 223 {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ 224 {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ 225 {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ 226 {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ 227 {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ 228 {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ 229 {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ 230 {UART5_TX, (M0)}, /* UART5_TX */ 231 {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ 232 {UART5_RTS, (M0)}, /* UART5_RTS */ 233 {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ 234 {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ 235 {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ 236 {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ 237 {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ 238 {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ 239 {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ 240 {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ 241 {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ 242 {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ 243 {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ 244 {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ 245 {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ 246 {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ 247 {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ 248 {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ 249 {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ 250 {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ 251 {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ 252 253 }; 254 255 const struct pad_conf_entry wkup_padconf_array_non_essential[] = { 256 257 /* 258 * This pad keeps C2C Module always enabled. 259 * Putting this in safe mode do not cause the issue. 260 * C2C driver could enable this mux setting if needed. 261 */ 262 {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ 263 {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ 264 {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ 265 {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ 266 {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ 267 {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ 268 {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ 269 {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ 270 {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ 271 {JTAG_TDO, (M0)}, /* JTAG_TDO */ 272 {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ 273 {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ 274 {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ 275 {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ 276 {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ 277 {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ 278 {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ 279 {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ 280 {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ 281 {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ 282 {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ 283 {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ 284 {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ 285 {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ 286 {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ 287 {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ 288 {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ 289 290 }; 291 292 #endif /* _EVM4430_MUX_DATA_H */ 293