1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * Aneesh V <aneesh@ti.com> 5 * Steve Sakoman <steve@sakoman.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <palmas.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/mmc_host_def.h> 13 #include <tca642x.h> 14 15 #include "mux_data.h" 16 17 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) 18 #include <usb.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/ehci.h> 22 #include <asm/ehci-omap.h> 23 #include <asm/arch/sata.h> 24 25 #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) 26 #define DIE_ID_REG_OFFSET 0x200 27 28 #endif 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 const struct omap_sysinfo sysinfo = { 33 "Board: OMAP5432 uEVM\n" 34 }; 35 36 /** 37 * @brief tca642x_init - uEVM default values for the GPIO expander 38 * input reg, output reg, polarity reg, configuration reg 39 */ 40 struct tca642x_bank_info tca642x_init[] = { 41 { .input_reg = 0x00, 42 .output_reg = 0x04, 43 .polarity_reg = 0x00, 44 .configuration_reg = 0x80 }, 45 { .input_reg = 0x00, 46 .output_reg = 0x00, 47 .polarity_reg = 0x00, 48 .configuration_reg = 0xff }, 49 { .input_reg = 0x00, 50 .output_reg = 0x00, 51 .polarity_reg = 0x00, 52 .configuration_reg = 0x40 }, 53 }; 54 55 /** 56 * @brief board_init 57 * 58 * @return 0 59 */ 60 int board_init(void) 61 { 62 gpmc_init(); 63 gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; 64 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 65 66 tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); 67 68 return 0; 69 } 70 71 int board_late_init(void) 72 { 73 omap_sata_init(); 74 return 0; 75 } 76 77 int board_eth_init(bd_t *bis) 78 { 79 return 0; 80 } 81 82 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) 83 static void enable_host_clocks(void) 84 { 85 int auxclk; 86 int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | 87 OPTFCLKEN_HSIC480M_P3_CLK | 88 OPTFCLKEN_HSIC60M_P2_CLK | 89 OPTFCLKEN_HSIC480M_P2_CLK | 90 OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); 91 92 /* Enable port 2 and 3 clocks*/ 93 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); 94 95 /* Enable port 2 and 3 usb host ports tll clocks*/ 96 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, 97 (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); 98 #ifdef CONFIG_USB_XHCI_OMAP 99 /* Enable the USB OTG Super speed clocks */ 100 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, 101 (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW)); 102 #endif 103 104 auxclk = readl((*prcm)->scrm_auxclk1); 105 /* Request auxilary clock */ 106 auxclk |= AUXCLK_ENABLE_MASK; 107 writel(auxclk, (*prcm)->scrm_auxclk1); 108 } 109 #endif 110 111 /** 112 * @brief misc_init_r - Configure EVM board specific configurations 113 * such as power configurations, ethernet initialization as phase2 of 114 * boot sequence 115 * 116 * @return 0 117 */ 118 int misc_init_r(void) 119 { 120 int reg; 121 uint8_t device_mac[6]; 122 123 #ifdef CONFIG_PALMAS_POWER 124 palmas_init_settings(); 125 #endif 126 127 if (!getenv("usbethaddr")) { 128 reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; 129 130 /* 131 * create a fake MAC address from the processor ID code. 132 * first byte is 0x02 to signify locally administered. 133 */ 134 device_mac[0] = 0x02; 135 device_mac[1] = readl(reg + 0x10) & 0xff; 136 device_mac[2] = readl(reg + 0xC) & 0xff; 137 device_mac[3] = readl(reg + 0x8) & 0xff; 138 device_mac[4] = readl(reg) & 0xff; 139 device_mac[5] = (readl(reg) >> 8) & 0xff; 140 141 eth_setenv_enetaddr("usbethaddr", device_mac); 142 } 143 144 return 0; 145 } 146 147 void set_muxconf_regs_essential(void) 148 { 149 do_set_mux((*ctrl)->control_padconf_core_base, 150 core_padconf_array_essential, 151 sizeof(core_padconf_array_essential) / 152 sizeof(struct pad_conf_entry)); 153 154 do_set_mux((*ctrl)->control_padconf_wkup_base, 155 wkup_padconf_array_essential, 156 sizeof(wkup_padconf_array_essential) / 157 sizeof(struct pad_conf_entry)); 158 } 159 160 void set_muxconf_regs_non_essential(void) 161 { 162 do_set_mux((*ctrl)->control_padconf_core_base, 163 core_padconf_array_non_essential, 164 sizeof(core_padconf_array_non_essential) / 165 sizeof(struct pad_conf_entry)); 166 167 do_set_mux((*ctrl)->control_padconf_wkup_base, 168 wkup_padconf_array_non_essential, 169 sizeof(wkup_padconf_array_non_essential) / 170 sizeof(struct pad_conf_entry)); 171 } 172 173 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 174 int board_mmc_init(bd_t *bis) 175 { 176 omap_mmc_init(0, 0, 0, -1, -1); 177 omap_mmc_init(1, 0, 0, -1, -1); 178 return 0; 179 } 180 #endif 181 182 #ifdef CONFIG_USB_EHCI 183 static struct omap_usbhs_board_data usbhs_bdata = { 184 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, 185 .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, 186 .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, 187 }; 188 189 int ehci_hcd_init(int index, enum usb_init_type init, 190 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 191 { 192 int ret; 193 194 enable_host_clocks(); 195 196 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 197 if (ret < 0) { 198 puts("Failed to initialize ehci\n"); 199 return ret; 200 } 201 202 return 0; 203 } 204 205 int ehci_hcd_stop(void) 206 { 207 int ret; 208 209 ret = omap_ehci_hcd_stop(); 210 return ret; 211 } 212 213 void usb_hub_reset_devices(int port) 214 { 215 /* The LAN9730 needs to be reset after the port power has been set. */ 216 if (port == 3) { 217 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); 218 udelay(10); 219 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); 220 } 221 } 222 #endif 223 224 #ifdef CONFIG_USB_XHCI_OMAP 225 /** 226 * @brief board_usb_init - Configure EVM board specific configurations 227 * for the LDO's and clocks for the USB blocks. 228 * 229 * @return 0 230 */ 231 int board_usb_init(int index, enum usb_init_type init) 232 { 233 int ret; 234 #ifdef CONFIG_PALMAS_USB_SS_PWR 235 ret = palmas_enable_ss_ldo(); 236 #endif 237 238 enable_host_clocks(); 239 240 return 0; 241 } 242 #endif 243