1 /* 2 * (C) Copyright 2010 3 * Texas Instruments Incorporated, <www.ti.com> 4 * Aneesh V <aneesh@ti.com> 5 * Steve Sakoman <steve@sakoman.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <palmas.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/mmc_host_def.h> 13 #include <tca642x.h> 14 15 #include "mux_data.h" 16 17 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) 18 #include <usb.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/ehci.h> 22 #include <asm/ehci-omap.h> 23 24 #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) 25 #define DIE_ID_REG_OFFSET 0x200 26 27 #endif 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 const struct omap_sysinfo sysinfo = { 32 "Board: OMAP5432 uEVM\n" 33 }; 34 35 /** 36 * @brief tca642x_init - uEVM default values for the GPIO expander 37 * input reg, output reg, polarity reg, configuration reg 38 */ 39 struct tca642x_bank_info tca642x_init[] = { 40 { .input_reg = 0x00, 41 .output_reg = 0x04, 42 .polarity_reg = 0x00, 43 .configuration_reg = 0x80 }, 44 { .input_reg = 0x00, 45 .output_reg = 0x00, 46 .polarity_reg = 0x00, 47 .configuration_reg = 0xff }, 48 { .input_reg = 0x00, 49 .output_reg = 0x00, 50 .polarity_reg = 0x00, 51 .configuration_reg = 0x40 }, 52 }; 53 54 /** 55 * @brief board_init 56 * 57 * @return 0 58 */ 59 int board_init(void) 60 { 61 gpmc_init(); 62 gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; 63 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 64 65 tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); 66 67 return 0; 68 } 69 70 int board_eth_init(bd_t *bis) 71 { 72 return 0; 73 } 74 75 #if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) 76 static void enable_host_clocks(void) 77 { 78 int auxclk; 79 int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | 80 OPTFCLKEN_HSIC480M_P3_CLK | 81 OPTFCLKEN_HSIC60M_P2_CLK | 82 OPTFCLKEN_HSIC480M_P2_CLK | 83 OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); 84 85 /* Enable port 2 and 3 clocks*/ 86 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); 87 88 /* Enable port 2 and 3 usb host ports tll clocks*/ 89 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, 90 (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); 91 #ifdef CONFIG_USB_XHCI_OMAP 92 /* Enable the USB OTG Super speed clocks */ 93 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, 94 (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW)); 95 #endif 96 97 auxclk = readl((*prcm)->scrm_auxclk1); 98 /* Request auxilary clock */ 99 auxclk |= AUXCLK_ENABLE_MASK; 100 writel(auxclk, (*prcm)->scrm_auxclk1); 101 } 102 #endif 103 104 /** 105 * @brief misc_init_r - Configure EVM board specific configurations 106 * such as power configurations, ethernet initialization as phase2 of 107 * boot sequence 108 * 109 * @return 0 110 */ 111 int misc_init_r(void) 112 { 113 int reg; 114 uint8_t device_mac[6]; 115 116 #ifdef CONFIG_PALMAS_POWER 117 palmas_init_settings(); 118 #endif 119 120 if (!getenv("usbethaddr")) { 121 reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; 122 123 /* 124 * create a fake MAC address from the processor ID code. 125 * first byte is 0x02 to signify locally administered. 126 */ 127 device_mac[0] = 0x02; 128 device_mac[1] = readl(reg + 0x10) & 0xff; 129 device_mac[2] = readl(reg + 0xC) & 0xff; 130 device_mac[3] = readl(reg + 0x8) & 0xff; 131 device_mac[4] = readl(reg) & 0xff; 132 device_mac[5] = (readl(reg) >> 8) & 0xff; 133 134 eth_setenv_enetaddr("usbethaddr", device_mac); 135 } 136 137 return 0; 138 } 139 140 void set_muxconf_regs_essential(void) 141 { 142 do_set_mux((*ctrl)->control_padconf_core_base, 143 core_padconf_array_essential, 144 sizeof(core_padconf_array_essential) / 145 sizeof(struct pad_conf_entry)); 146 147 do_set_mux((*ctrl)->control_padconf_wkup_base, 148 wkup_padconf_array_essential, 149 sizeof(wkup_padconf_array_essential) / 150 sizeof(struct pad_conf_entry)); 151 } 152 153 void set_muxconf_regs_non_essential(void) 154 { 155 do_set_mux((*ctrl)->control_padconf_core_base, 156 core_padconf_array_non_essential, 157 sizeof(core_padconf_array_non_essential) / 158 sizeof(struct pad_conf_entry)); 159 160 do_set_mux((*ctrl)->control_padconf_wkup_base, 161 wkup_padconf_array_non_essential, 162 sizeof(wkup_padconf_array_non_essential) / 163 sizeof(struct pad_conf_entry)); 164 } 165 166 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 167 int board_mmc_init(bd_t *bis) 168 { 169 omap_mmc_init(0, 0, 0, -1, -1); 170 omap_mmc_init(1, 0, 0, -1, -1); 171 return 0; 172 } 173 #endif 174 175 #ifdef CONFIG_USB_EHCI 176 static struct omap_usbhs_board_data usbhs_bdata = { 177 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, 178 .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, 179 .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, 180 }; 181 182 int ehci_hcd_init(int index, enum usb_init_type init, 183 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 184 { 185 int ret; 186 187 enable_host_clocks(); 188 189 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 190 if (ret < 0) { 191 puts("Failed to initialize ehci\n"); 192 return ret; 193 } 194 195 return 0; 196 } 197 198 int ehci_hcd_stop(void) 199 { 200 int ret; 201 202 ret = omap_ehci_hcd_stop(); 203 return ret; 204 } 205 206 void usb_hub_reset_devices(int port) 207 { 208 /* The LAN9730 needs to be reset after the port power has been set. */ 209 if (port == 3) { 210 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); 211 udelay(10); 212 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); 213 } 214 } 215 #endif 216 217 #ifdef CONFIG_USB_XHCI_OMAP 218 /** 219 * @brief board_usb_init - Configure EVM board specific configurations 220 * for the LDO's and clocks for the USB blocks. 221 * 222 * @return 0 223 */ 224 int board_usb_init(int index, enum usb_init_type init) 225 { 226 int ret; 227 #ifdef CONFIG_PALMAS_USB_SS_PWR 228 ret = palmas_enable_ss_ldo(); 229 #endif 230 231 enable_host_clocks(); 232 233 return 0; 234 } 235 #endif 236