1 /* 2 * K2G EVM: Pinmux configuration 3 * 4 * (C) Copyright 2015 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/mux-k2g.h> 13 #include <asm/arch/hardware.h> 14 15 struct pin_cfg k2g_evm_pin_cfg[] = { 16 /* GPMC */ 17 { 0, MODE(0) }, /* GPMCAD0 */ 18 { 1, MODE(0) }, /* GPMCAD1 */ 19 { 2, MODE(0) }, /* GPMCAD2 */ 20 { 3, MODE(0) }, /* GPMCAD3 */ 21 { 4, MODE(0) }, /* GPMCAD4 */ 22 { 5, MODE(0) }, /* GPMCAD5 */ 23 { 6, MODE(0) }, /* GPMCAD6 */ 24 { 7, MODE(0) }, /* GPMCAD7 */ 25 { 8, MODE(0) }, /* GPMCAD8 */ 26 { 9, MODE(0) }, /* GPMCAD9 */ 27 { 10, MODE(0) }, /* GPMCAD10 */ 28 { 11, MODE(0) }, /* GPMCAD11 */ 29 { 12, MODE(0) }, /* GPMCAD12 */ 30 { 13, MODE(0) }, /* GPMCAD13 */ 31 { 14, MODE(0) }, /* GPMCAD14 */ 32 { 15, MODE(0) }, /* GPMCAD15 */ 33 { 17, MODE(0) }, /* GPMCADVNALE */ 34 { 18, MODE(0) }, /* GPMCOENREN */ 35 { 19, MODE(0) }, /* GPMCWEN */ 36 { 20, MODE(0) }, /* GPMCBE0NCLE */ 37 { 22, MODE(0) }, /* GPMCWAIT0 */ 38 { 24, MODE(0) }, /* GPMCWPN */ 39 { 26, MODE(0) }, /* GPMCCSN0 */ 40 41 /* GPIOs */ 42 { 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */ 43 { 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */ 44 { 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */ 45 { 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */ 46 { 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */ 47 { 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */ 48 { 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */ 49 { 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */ 50 { 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */ 51 { 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */ 52 { 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */ 53 { 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */ 54 { 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/ 55 { 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */ 56 { 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */ 57 { 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */ 58 { 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */ 59 { 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */ 60 61 /* MLB */ 62 { 23, MODE(2) }, /* SOC_MLBCLK */ 63 { 25, MODE(2) }, /* SOC_MLBSIG */ 64 { 27, MODE(2) }, /* SOC_MLBDAT */ 65 66 /* DSS */ 67 { 30, MODE(0) }, /* SOC_DSSDATA23 */ 68 { 31, MODE(0) }, /* SOC_DSSDATA22 */ 69 { 32, MODE(0) }, /* SOC_DSSDATA21 */ 70 { 33, MODE(0) }, /* SOC_DSSDATA20 */ 71 { 34, MODE(0) }, /* SOC_DSSDATA19 */ 72 { 35, MODE(0) }, /* SOC_DSSDATA18 */ 73 { 36, MODE(0) }, /* SOC_DSSDATA17 */ 74 { 37, MODE(0) }, /* SOC_DSSDATA16 */ 75 { 38, MODE(0) }, /* SOC_DSSDATA15 */ 76 { 39, MODE(0) }, /* SOC_DSSDATA14 */ 77 { 40, MODE(0) }, /* SOC_DSSDATA13 */ 78 { 41, MODE(0) }, /* SOC_DSSDATA12 */ 79 { 42, MODE(0) }, /* SOC_DSSDATA11 */ 80 { 43, MODE(0) }, /* SOC_DSSDATA10 */ 81 { 44, MODE(0) }, /* SOC_DSSDATA9 */ 82 { 45, MODE(0) }, /* SOC_DSSDATA8 */ 83 { 46, MODE(0) }, /* SOC_DSSDATA7 */ 84 { 47, MODE(0) }, /* SOC_DSSDATA6 */ 85 { 48, MODE(0) }, /* SOC_DSSDATA5 */ 86 { 49, MODE(0) }, /* SOC_DSSDATA4 */ 87 { 50, MODE(0) }, /* SOC_DSSDATA3 */ 88 { 51, MODE(0) }, /* SOC_DSSDATA2 */ 89 { 52, MODE(0) }, /* SOC_DSSDATA1 */ 90 { 53, MODE(0) }, /* SOC_DSSDATA0 */ 91 { 54, MODE(0) }, /* SOC_DSSVSYNC */ 92 { 55, MODE(0) }, /* SOC_DSSHSYNC */ 93 { 56, MODE(0) }, /* SOC_DSSPCLK */ 94 { 57, MODE(0) }, /* SOC_DSS_DE */ 95 { 58, MODE(0) }, /* SOC_DSS_FID */ 96 { 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */ 97 98 /* MMC1 */ 99 { 59, MODE(0) }, /* SOC_MMC1_DAT7 */ 100 { 60, MODE(0) }, /* SOC_MMC1_DAT6 */ 101 { 61, MODE(0) }, /* SOC_MMC1_DAT5 */ 102 { 62, MODE(0) }, /* SOC_MMC1_DAT4 */ 103 { 63, MODE(0) }, /* SOC_MMC1_DAT3 */ 104 { 64, MODE(0) }, /* SOC_MMC1_DAT2 */ 105 { 65, MODE(0) }, /* SOC_MMC1_DAT1 */ 106 { 66, MODE(0) }, /* SOC_MMC1_DAT0 */ 107 { 67, MODE(0) }, /* SOC_MMC1_CLK */ 108 { 68, MODE(0) }, /* SOC_MMC1_CMD */ 109 { 69, MODE(0) }, /* MMC1SDCD TP125 */ 110 { 70, MODE(0) }, /* SOC_MMC1_SDWP */ 111 { 71, MODE(0) }, /* MMC1POW TP124 */ 112 113 /* RGMII */ 114 { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ 115 { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ 116 { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ 117 { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ 118 { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ 119 { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ 120 { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ 121 { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ 122 { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ 123 { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ 124 { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ 125 { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ 126 { 98, MODE(0) }, /* SOC_MDIO_DATA */ 127 { 99, MODE(0) }, /* SOC_MDIO_CLK */ 128 129 /* PWM */ 130 { 73, MODE(4) }, /* SOC_EHRPWM3A */ 131 { 74, MODE(4) }, /* SOC_EHRPWM3B */ 132 { 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */ 133 { 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */ 134 { 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */ 135 { 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */ 136 { 199, MODE(4) }, /* SOC_EHRPWM4A */ 137 { 200, MODE(4) }, /* SOC_EHRPWM4B */ 138 { 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */ 139 { 219, MODE(4) }, /* SOC_EHRPWM5A */ 140 { 220, MODE(4) }, /* SOC_EHRPWM5B */ 141 { 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */ 142 143 /* SPI3 */ 144 { 86, MODE(1) }, /* SOC_SPI3_SCS0 */ 145 { 88, MODE(1) }, /* SOC_SPI3_CLK */ 146 { 89, MODE(1) }, /* SOC_SPI3_MISO */ 147 { 90, MODE(1) }, /* SOC_SPI3_MOSI */ 148 149 /* CLK */ 150 { 97, MODE(0) }, /* SMD - TP132 */ 151 152 /* SPI0 */ 153 { 100, MODE(0) }, /* SOC_SPI0_SCS0 */ 154 { 101, MODE(0) }, /* SOC_SPI0_SCS1 */ 155 { 102, MODE(0) }, /* SOC_SPI0_CLK */ 156 { 103, MODE(0) }, /* SOC_SPI0_MISO */ 157 { 104, MODE(0) }, /* SOC_SPI0_MOSI */ 158 159 /* SPI1 NORFLASH */ 160 { 105, MODE(0) }, /* SOC_SPI1_SCS0 */ 161 { 107, MODE(0) }, /* SOC_SPI1_CLK */ 162 { 108, MODE(0) }, /* SOC_SPI1_MISO */ 163 { 109, MODE(0) }, /* SOC_SPI1_MOSI */ 164 165 /* SPI2 */ 166 { 110, MODE(0) }, /* SOC_SPI2_SCS0 */ 167 { 111, MODE(1) }, /* SOC_HOUT */ 168 { 112, MODE(0) }, /* SOC_SPI2_CLK */ 169 { 113, MODE(0) }, /* SOC_SPI2_MISO */ 170 { 114, MODE(0) }, /* SOC_SPI2_MOSI */ 171 172 /* UART0 */ 173 { 115, MODE(0) }, /* SOC_UART0_RXD */ 174 { 116, MODE(0) }, /* SOC_UART0_TXD */ 175 { 117, MODE(0) }, /* SOC_UART0_CTSn */ 176 { 118, MODE(0) }, /* SOC_UART0_RTSn */ 177 178 /* UART1 */ 179 { 119, MODE(0) }, /* SOC_UART1_RXD */ 180 { 120, MODE(0) }, /* SOC_UART1_TXD */ 181 { 121, MODE(0) }, /* SOC_UART1_CTSn */ 182 { 122, MODE(0) }, /* SOC_UART1_RTSn */ 183 184 /* UART2 */ 185 { 123, MODE(0) }, /* SOC_UART2_RXD */ 186 { 124, MODE(0) }, /* SOC_UART2_TXD */ 187 { 125, MODE(0) }, /* UART0_TXVR_EN */ 188 { 126, MODE(4) }, /* SOC_CPTS_TS_COMP */ 189 190 /* DCAN */ 191 { 127, MODE(0) }, /* SOC_DCAN0_TX */ 192 { 128, MODE(0) }, /* SOC_DCAN0_RX */ 193 { 137, MODE(1) }, /* SOC_DCAN1_TX */ 194 { 138, MODE(1) }, /* SOC_DCAN1_RX */ 195 196 /* QSPI */ 197 { 129, MODE(0) }, /* SOC_QSPI_CLK */ 198 { 130, MODE(0) }, /* SOC_QSPI_RTCLK */ 199 { 131, MODE(0) }, /* SOC_QSPI_D0 */ 200 { 132, MODE(0) }, /* SOC_QSPI_D1 */ 201 { 133, MODE(0) }, /* SOC_QSPI_D2 */ 202 { 134, MODE(0) }, /* SOC_QSPI_D3 */ 203 { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ 204 { 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */ 205 206 /* MCASP2 */ 207 { 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */ 208 { 140, MODE(4) }, /* SOC_MCASP2AXR1 */ 209 { 141, MODE(4) }, /* SOC_MCASP2AXR2 */ 210 { 142, MODE(4) }, /* SOC_MCASP2AXR3 */ 211 { 143, MODE(4) }, /* SOC_MCASP2AXR4 */ 212 { 144, MODE(4) }, /* SOC_MCASP2AXR5 */ 213 { 145, MODE(4) }, /* SOC_McASP2ACLKR */ 214 { 146, MODE(4) }, /* SOC_McASP2FSR */ 215 { 147, MODE(4) }, /* SOC_McASP2AHCLKR */ 216 { 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */ 217 { 149, MODE(4) }, /* SOC_McASP2FSX */ 218 { 150, MODE(4) }, /* SOC_McASP2AHCLKX */ 219 { 151, MODE(4) }, /* SOC_McASP2ACLKX */ 220 221 /* MCASP1 */ 222 { 152, MODE(4) }, /* SOC_MCASP1ACLKR */ 223 { 153, MODE(4) }, /* SOC_MCASP1FSR */ 224 { 154, MODE(4) }, /* SOC_MCASP1AHCLKR */ 225 { 155, MODE(4) }, /* SOC_MCASP1ACLKX */ 226 { 156, MODE(4) }, /* SOC_MCASP1FSX */ 227 { 157, MODE(4) }, /* SOC_MCASP1AHCLKX */ 228 { 158, MODE(4) }, /* SOC_MCASP1AMUTE */ 229 { 159, MODE(4) }, /* SOC_MCASP1AXR0 */ 230 { 160, MODE(4) }, /* SOC_MCASP1AXR1 */ 231 { 161, MODE(4) }, /* SOC_MCASP1AXR2 */ 232 { 162, MODE(4) }, /* SOC_MCASP1AXR3 */ 233 { 163, MODE(4) }, /* SOC_MCASP1AXR4 */ 234 { 164, MODE(4) }, /* SOC_MCASP1AXR5 */ 235 { 165, MODE(4) }, /* SOC_MCASP1AXR6 */ 236 { 166, MODE(4) }, /* SOC_MCASP1AXR7 */ 237 { 167, MODE(4) }, /* SOC_MCASP1AXR8 */ 238 { 168, MODE(4) }, /* SOC_MCASP1AXR9 */ 239 240 /* MCASP0 */ 241 { 169, MODE(4) }, /* SOC_MCASP0AMUTE */ 242 { 170, MODE(4) }, /* SOC_MCASP0ACLKR */ 243 { 171, MODE(4) }, /* SOC_MCASP0FSR */ 244 { 172, MODE(4) }, /* SOC_MCASP0AHCLKR */ 245 { 173, MODE(4) }, /* SOC_MCASP0ACLKX */ 246 { 174, MODE(4) }, /* SOC_MCASP0FSX */ 247 { 175, MODE(4) }, /* SOC_MCASP0AHCLKX */ 248 { 176, MODE(4) }, /* SOC_MCASP0AXR0 */ 249 { 177, MODE(4) }, /* SOC_MCASP0AXR1 */ 250 { 178, MODE(4) }, /* SOC_MCASP0AXR2 */ 251 { 179, MODE(4) }, /* SOC_MCASP0AXR3 */ 252 { 180, MODE(4) }, /* SOC_MCASP0AXR4 */ 253 { 181, MODE(4) }, /* SOC_MCASP0AXR5 */ 254 { 182, MODE(4) }, /* SOC_MCASP0AXR6 */ 255 { 183, MODE(4) }, /* SOC_MCASP0AXR7 */ 256 { 184, MODE(4) }, /* SOC_MCASP0AXR8 */ 257 { 185, MODE(4) }, /* SOC_MCASP0AXR9 */ 258 { 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */ 259 { 188, MODE(4) }, /* SOC_MCASP0AXR12 */ 260 { 189, MODE(4) }, /* SOC_MCASP0AXR13 */ 261 { 190, MODE(4) }, /* SOC_MCASP0AXR14 */ 262 { 191, MODE(4) }, /* SOC_MCASP0AXR15 */ 263 264 /* MMC0 */ 265 { 192, MODE(2) }, /* SOC_MMC0_DAT3 */ 266 { 193, MODE(2) }, /* SOC_MMC0_DAT2 */ 267 { 194, MODE(2) }, /* SOC_MMC0_DAT1 */ 268 { 195, MODE(2) }, /* SOC_MMC0_DAT0 */ 269 { 196, MODE(2) }, /* SOC_MMC0_CLK */ 270 { 197, MODE(2) }, /* SOC_MMC0_CMD */ 271 { 187, MODE(2) }, /* SOC_MMC0_SDCD */ 272 273 /* McBSP */ 274 { 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */ 275 { 29, MODE(2) }, /* SOC_TIMO1 */ 276 { 210, MODE(2) }, /* SOC_MCBSPDR */ 277 { 211, MODE(2) }, /* SOC_MCBSPDX */ 278 { 212, MODE(2) }, /* SOC_MCBSPFSX */ 279 { 213, MODE(2) }, /* SOC_MCBSPCLKX */ 280 { 214, MODE(2) }, /* SOC_MCBSPFSR */ 281 { 215, MODE(2) }, /* SOC_MCBSPCLKR */ 282 283 /* I2C */ 284 { 223, MODE(0) }, /* SOC_I2C0_SCL */ 285 { 224, MODE(0) }, /* SOC_I2C0_SDA */ 286 { 225, MODE(0) }, /* SOC_I2C1_SCL */ 287 { 226, MODE(0) }, /* SOC_I2C1_SDA */ 288 { 227, MODE(0) }, /* SOC_I2C2_SCL */ 289 { 228, MODE(0) }, /* SOC_I2C2_SDA */ 290 { 229, MODE(0) }, /* NMIz */ 291 { 230, MODE(0) }, /* LRESETz */ 292 { 231, MODE(0) }, /* LRESETNMIENz */ 293 294 { 235, MODE(0) }, 295 { 236, MODE(0) }, 296 { 237, MODE(0) }, 297 { 238, MODE(0) }, 298 { 239, MODE(0) }, 299 { 240, MODE(0) }, 300 { 241, MODE(0) }, 301 { 242, MODE(0) }, 302 { 243, MODE(0) }, 303 { 244, MODE(0) }, 304 305 { 258, MODE(0) }, /* USB0DRVVBUS */ 306 { 259, MODE(0) }, /* USB1DRVVBUS */ 307 { MAX_PIN_N, } 308 }; 309 310 void k2g_mux_config(void) 311 { 312 configure_pin_mux(k2g_evm_pin_cfg); 313 } 314