1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2345af534SHao Zhang /* 3345af534SHao Zhang * Keystone2: DDR3 initialization 4345af534SHao Zhang * 5345af534SHao Zhang * (C) Copyright 2014 6345af534SHao Zhang * Texas Instruments Incorporated, <www.ti.com> 7345af534SHao Zhang */ 8345af534SHao Zhang 9345af534SHao Zhang #include <common.h> 10345af534SHao Zhang #include "ddr3_cfg.h" 11345af534SHao Zhang #include <asm/arch/ddr3.h> 12345af534SHao Zhang 13345af534SHao Zhang static struct pll_init_data ddr3_400 = DDR3_PLL_400; 14345af534SHao Zhang ddr3_init(void)1566c98a0cSVitaly Andrianovu32 ddr3_init(void) 16345af534SHao Zhang { 17345af534SHao Zhang init_pll(&ddr3_400); 18345af534SHao Zhang 19345af534SHao Zhang /* No SO-DIMM, 2GB discreet DDR */ 20345af534SHao Zhang printf("DRAM: 2 GiB\n"); 21345af534SHao Zhang 22345af534SHao Zhang /* Reset DDR3 PHY after PLL enabled */ 23345af534SHao Zhang ddr3_reset_ddrphy(); 24345af534SHao Zhang 25345af534SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); 26345af534SHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); 27345af534SHao Zhang 2866c98a0cSVitaly Andrianov return 2; 29345af534SHao Zhang } 30