1345af534SHao Zhang /* 2345af534SHao Zhang * Keystone2: DDR3 initialization 3345af534SHao Zhang * 4345af534SHao Zhang * (C) Copyright 2014 5345af534SHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6345af534SHao Zhang * 7345af534SHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8345af534SHao Zhang */ 9345af534SHao Zhang 10345af534SHao Zhang #include <common.h> 11345af534SHao Zhang #include "ddr3_cfg.h" 12345af534SHao Zhang #include <asm/arch/ddr3.h> 13345af534SHao Zhang 14345af534SHao Zhang static struct pll_init_data ddr3_400 = DDR3_PLL_400; 15345af534SHao Zhang 16*66c98a0cSVitaly Andrianov u32 ddr3_init(void) 17345af534SHao Zhang { 18345af534SHao Zhang init_pll(&ddr3_400); 19345af534SHao Zhang 20345af534SHao Zhang /* No SO-DIMM, 2GB discreet DDR */ 21345af534SHao Zhang printf("DRAM: 2 GiB\n"); 22345af534SHao Zhang 23345af534SHao Zhang /* Reset DDR3 PHY after PLL enabled */ 24345af534SHao Zhang ddr3_reset_ddrphy(); 25345af534SHao Zhang 26345af534SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); 27345af534SHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); 28345af534SHao Zhang 29*66c98a0cSVitaly Andrianov return 2; 30345af534SHao Zhang } 31