1*345af534SHao Zhang /* 2*345af534SHao Zhang * Keystone2: DDR3 initialization 3*345af534SHao Zhang * 4*345af534SHao Zhang * (C) Copyright 2014 5*345af534SHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6*345af534SHao Zhang * 7*345af534SHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8*345af534SHao Zhang */ 9*345af534SHao Zhang 10*345af534SHao Zhang #include <common.h> 11*345af534SHao Zhang #include "ddr3_cfg.h" 12*345af534SHao Zhang #include <asm/arch/ddr3.h> 13*345af534SHao Zhang 14*345af534SHao Zhang static int ddr3_size; 15*345af534SHao Zhang static struct pll_init_data ddr3_400 = DDR3_PLL_400; 16*345af534SHao Zhang 17*345af534SHao Zhang void ddr3_init(void) 18*345af534SHao Zhang { 19*345af534SHao Zhang init_pll(&ddr3_400); 20*345af534SHao Zhang 21*345af534SHao Zhang /* No SO-DIMM, 2GB discreet DDR */ 22*345af534SHao Zhang printf("DRAM: 2 GiB\n"); 23*345af534SHao Zhang ddr3_size = 2; 24*345af534SHao Zhang 25*345af534SHao Zhang /* Reset DDR3 PHY after PLL enabled */ 26*345af534SHao Zhang ddr3_reset_ddrphy(); 27*345af534SHao Zhang 28*345af534SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); 29*345af534SHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); 30*345af534SHao Zhang } 31*345af534SHao Zhang 32*345af534SHao Zhang /** 33*345af534SHao Zhang * ddr3_get_size - return ddr3 size in GiB 34*345af534SHao Zhang */ 35*345af534SHao Zhang int ddr3_get_size(void) 36*345af534SHao Zhang { 37*345af534SHao Zhang return ddr3_size; 38*345af534SHao Zhang } 39