1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * K2G: DDR3 initialization 4 * 5 * (C) Copyright 2015 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #include <common.h> 10 #include "ddr3_cfg.h" 11 #include <asm/arch/ddr3.h> 12 #include <asm/arch/hardware.h> 13 #include "board.h" 14 15 /* K2G GP EVM DDR3 Configuration */ 16 static struct ddr3_phy_config ddr3phy_800_2g = { 17 .pllcr = 0x000DC000ul, 18 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 19 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), 20 .ptr0 = 0x42C21590ul, 21 .ptr1 = 0xD05612C0ul, 22 .ptr2 = 0, 23 .ptr3 = 0x06C30D40ul, 24 .ptr4 = 0x06413880ul, 25 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 26 .dcr_val = ((1 << 10)), 27 .dtpr0 = 0x550F6644ul, 28 .dtpr1 = 0x328341E0ul, 29 .dtpr2 = 0x50022A00ul, 30 .mr0 = 0x00001430ul, 31 .mr1 = 0x00000006ul, 32 .mr2 = 0x00000000ul, 33 .dtcr = 0x710035C7ul, 34 .pgcr2 = 0x00F03D09ul, 35 .zq0cr1 = 0x0001005Dul, 36 .zq1cr1 = 0x0001005Bul, 37 .zq2cr1 = 0x0001005Bul, 38 .pir_v1 = 0x00000033ul, 39 .datx8_2_mask = 0, 40 .datx8_2_val = 0, 41 .datx8_3_mask = 0, 42 .datx8_3_val = 0, 43 .datx8_4_mask = 0, 44 .datx8_4_val = ((1 << 0)), 45 .datx8_5_mask = DXEN_MASK, 46 .datx8_5_val = 0, 47 .datx8_6_mask = DXEN_MASK, 48 .datx8_6_val = 0, 49 .datx8_7_mask = DXEN_MASK, 50 .datx8_7_val = 0, 51 .datx8_8_mask = DXEN_MASK, 52 .datx8_8_val = 0, 53 .pir_v2 = 0x00000F81ul, 54 }; 55 56 static struct ddr3_phy_config ddr3phy_1066_2g = { 57 .pllcr = 0x000DC000ul, 58 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 59 .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), 60 .ptr0 = 0x42C21590ul, 61 .ptr1 = 0xD05612C0ul, 62 .ptr2 = 0, 63 .ptr3 = 0x0904111Dul, 64 .ptr4 = 0x0859A072ul, 65 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 66 .dcr_val = ((1 << 10)), 67 .dtpr0 = 0x6D147744ul, 68 .dtpr1 = 0x32845A80ul, 69 .dtpr2 = 0x50023600ul, 70 .mr0 = 0x00001830ul, 71 .mr1 = 0x00000006ul, 72 .mr2 = 0x00000000ul, 73 .dtcr = 0x710035C7ul, 74 .pgcr2 = 0x00F05159ul, 75 .zq0cr1 = 0x0001005Dul, 76 .zq1cr1 = 0x0001005Bul, 77 .zq2cr1 = 0x0001005Bul, 78 .pir_v1 = 0x00000033ul, 79 .datx8_2_mask = 0, 80 .datx8_2_val = 0, 81 .datx8_3_mask = 0, 82 .datx8_3_val = 0, 83 .datx8_4_mask = 0, 84 .datx8_4_val = ((1 << 0)), 85 .datx8_5_mask = DXEN_MASK, 86 .datx8_5_val = 0, 87 .datx8_6_mask = DXEN_MASK, 88 .datx8_6_val = 0, 89 .datx8_7_mask = DXEN_MASK, 90 .datx8_7_val = 0, 91 .datx8_8_mask = DXEN_MASK, 92 .datx8_8_val = 0, 93 .pir_v2 = 0x00000F81ul, 94 }; 95 96 static struct ddr3_emif_config ddr3_800_2g = { 97 .sdcfg = 0x62005662ul, 98 .sdtim1 = 0x0A385033ul, 99 .sdtim2 = 0x00001CA5ul, 100 .sdtim3 = 0x21ADFF32ul, 101 .sdtim4 = 0x533F067Ful, 102 .zqcfg = 0x70073200ul, 103 .sdrfc = 0x00000C34ul, 104 }; 105 106 static struct ddr3_emif_config ddr3_1066_2g = { 107 .sdcfg = 0x62005662ul, 108 .sdtim1 = 0x0E4C6843ul, 109 .sdtim2 = 0x00001CC6ul, 110 .sdtim3 = 0x323DFF32ul, 111 .sdtim4 = 0x533F08AFul, 112 .zqcfg = 0x70073200ul, 113 .sdrfc = 0x00001044ul, 114 }; 115 116 /* K2G ICE evm DDR3 Configuration */ 117 static struct ddr3_phy_config ddr3phy_800_512mb = { 118 .pllcr = 0x000DC000ul, 119 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 120 .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), 121 .ptr0 = 0x42C21590ul, 122 .ptr1 = 0xD05612C0ul, 123 .ptr2 = 0, 124 .ptr3 = 0x06C30D40ul, 125 .ptr4 = 0x06413880ul, 126 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 127 .dcr_val = ((1 << 10)), 128 .dtpr0 = 0x550E6644ul, 129 .dtpr1 = 0x32834200ul, 130 .dtpr2 = 0x50022A00ul, 131 .mr0 = 0x00001430ul, 132 .mr1 = 0x00000006ul, 133 .mr2 = 0x00000008ul, 134 .dtcr = 0x710035C7ul, 135 .pgcr2 = 0x00F03D09ul, 136 .zq0cr1 = 0x0001005Dul, 137 .zq1cr1 = 0x0001005Bul, 138 .zq2cr1 = 0x0001005Bul, 139 .pir_v1 = 0x00000033ul, 140 .datx8_2_mask = DXEN_MASK, 141 .datx8_2_val = 0, 142 .datx8_3_mask = DXEN_MASK, 143 .datx8_3_val = 0, 144 .datx8_4_mask = DXEN_MASK, 145 .datx8_4_val = 0, 146 .datx8_5_mask = DXEN_MASK, 147 .datx8_5_val = 0, 148 .datx8_6_mask = DXEN_MASK, 149 .datx8_6_val = 0, 150 .datx8_7_mask = DXEN_MASK, 151 .datx8_7_val = 0, 152 .datx8_8_mask = DXEN_MASK, 153 .datx8_8_val = 0, 154 .pir_v2 = 0x00000F81ul, 155 }; 156 157 static struct ddr3_emif_config ddr3_800_512mb = { 158 .sdcfg = 0x62006662ul, 159 .sdtim1 = 0x0A385033ul, 160 .sdtim2 = 0x00001CA5ul, 161 .sdtim3 = 0x21ADFF32ul, 162 .sdtim4 = 0x533F067Ful, 163 .zqcfg = 0x70073200ul, 164 .sdrfc = 0x00000C34ul, 165 }; 166 167 u32 ddr3_init(void) 168 { 169 /* Reset DDR3 PHY after PLL enabled */ 170 ddr3_reset_ddrphy(); 171 if (board_is_k2g_g1()) { 172 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g); 173 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g); 174 } else if (board_is_k2g_gp()) { 175 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); 176 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); 177 } else if (board_is_k2g_ice()) { 178 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb); 179 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb); 180 } 181 182 return 0; 183 } 184 185 inline int ddr3_get_size(void) 186 { 187 return 2; 188 } 189