1 /* 2 * K2G: DDR3 initialization 3 * 4 * (C) Copyright 2015 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include "ddr3_cfg.h" 12 #include <asm/arch/ddr3.h> 13 14 struct ddr3_phy_config ddr3phy_800_2g = { 15 .pllcr = 0x000DC000ul, 16 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 17 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), 18 .ptr0 = 0x42C21590ul, 19 .ptr1 = 0xD05612C0ul, 20 .ptr2 = 0, 21 .ptr3 = 0x06C30D40ul, 22 .ptr4 = 0x06413880ul, 23 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 24 .dcr_val = ((1 << 10)), 25 .dtpr0 = 0x550F6644ul, 26 .dtpr1 = 0x328341E0ul, 27 .dtpr2 = 0x50022A00ul, 28 .mr0 = 0x00001430ul, 29 .mr1 = 0x00000006ul, 30 .mr2 = 0x00000018ul, 31 .dtcr = 0x710035C7ul, 32 .pgcr2 = 0x00F03D09ul, 33 .zq0cr1 = 0x0001005Dul, 34 .zq1cr1 = 0x0001005Bul, 35 .zq2cr1 = 0x0001005Bul, 36 .pir_v1 = 0x00000033ul, 37 .pir_v2 = 0x00000F81ul, 38 }; 39 40 struct ddr3_emif_config ddr3_800_2g = { 41 .sdcfg = 0x62005662ul, 42 .sdtim1 = 0x0A385033ul, 43 .sdtim2 = 0x00001CA5ul, 44 .sdtim3 = 0x21ADFF32ul, 45 .sdtim4 = 0x533F067Ful, 46 .zqcfg = 0x70073200ul, 47 .sdrfc = 0x00000C34ul, 48 }; 49 50 u32 ddr3_init(void) 51 { 52 /* Reset DDR3 PHY after PLL enabled */ 53 ddr3_reset_ddrphy(); 54 55 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); 56 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); 57 58 return 0; 59 } 60 61 inline int ddr3_get_size(void) 62 { 63 return 2; 64 } 65