1 /* 2 * K2G: DDR3 initialization 3 * 4 * (C) Copyright 2015 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include "ddr3_cfg.h" 12 #include <asm/arch/ddr3.h> 13 #include <asm/arch/hardware.h> 14 #include "board.h" 15 16 /* K2G GP EVM DDR3 Configuration */ 17 static struct ddr3_phy_config ddr3phy_800_2g = { 18 .pllcr = 0x000DC000ul, 19 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 20 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), 21 .ptr0 = 0x42C21590ul, 22 .ptr1 = 0xD05612C0ul, 23 .ptr2 = 0, 24 .ptr3 = 0x06C30D40ul, 25 .ptr4 = 0x06413880ul, 26 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 27 .dcr_val = ((1 << 10)), 28 .dtpr0 = 0x550F6644ul, 29 .dtpr1 = 0x328341E0ul, 30 .dtpr2 = 0x50022A00ul, 31 .mr0 = 0x00001430ul, 32 .mr1 = 0x00000006ul, 33 .mr2 = 0x00000000ul, 34 .dtcr = 0x710035C7ul, 35 .pgcr2 = 0x00F03D09ul, 36 .zq0cr1 = 0x0001005Dul, 37 .zq1cr1 = 0x0001005Bul, 38 .zq2cr1 = 0x0001005Bul, 39 .pir_v1 = 0x00000033ul, 40 .datx8_2_mask = 0, 41 .datx8_2_val = 0, 42 .datx8_3_mask = 0, 43 .datx8_3_val = 0, 44 .datx8_4_mask = 0, 45 .datx8_4_val = ((1 << 0)), 46 .datx8_5_mask = DXEN_MASK, 47 .datx8_5_val = 0, 48 .datx8_6_mask = DXEN_MASK, 49 .datx8_6_val = 0, 50 .datx8_7_mask = DXEN_MASK, 51 .datx8_7_val = 0, 52 .datx8_8_mask = DXEN_MASK, 53 .datx8_8_val = 0, 54 .pir_v2 = 0x00000F81ul, 55 }; 56 57 static struct ddr3_phy_config ddr3phy_1066_2g = { 58 .pllcr = 0x000DC000ul, 59 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 60 .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), 61 .ptr0 = 0x42C21590ul, 62 .ptr1 = 0xD05612C0ul, 63 .ptr2 = 0, 64 .ptr3 = 0x0904111Dul, 65 .ptr4 = 0x0859A072ul, 66 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 67 .dcr_val = ((1 << 10)), 68 .dtpr0 = 0x6D147744ul, 69 .dtpr1 = 0x32845A80ul, 70 .dtpr2 = 0x50023600ul, 71 .mr0 = 0x00001830ul, 72 .mr1 = 0x00000006ul, 73 .mr2 = 0x00000000ul, 74 .dtcr = 0x710035C7ul, 75 .pgcr2 = 0x00F05159ul, 76 .zq0cr1 = 0x0001005Dul, 77 .zq1cr1 = 0x0001005Bul, 78 .zq2cr1 = 0x0001005Bul, 79 .pir_v1 = 0x00000033ul, 80 .datx8_2_mask = 0, 81 .datx8_2_val = 0, 82 .datx8_3_mask = 0, 83 .datx8_3_val = 0, 84 .datx8_4_mask = 0, 85 .datx8_4_val = ((1 << 0)), 86 .datx8_5_mask = DXEN_MASK, 87 .datx8_5_val = 0, 88 .datx8_6_mask = DXEN_MASK, 89 .datx8_6_val = 0, 90 .datx8_7_mask = DXEN_MASK, 91 .datx8_7_val = 0, 92 .datx8_8_mask = DXEN_MASK, 93 .datx8_8_val = 0, 94 .pir_v2 = 0x00000F81ul, 95 }; 96 97 static struct ddr3_emif_config ddr3_800_2g = { 98 .sdcfg = 0x62005662ul, 99 .sdtim1 = 0x0A385033ul, 100 .sdtim2 = 0x00001CA5ul, 101 .sdtim3 = 0x21ADFF32ul, 102 .sdtim4 = 0x533F067Ful, 103 .zqcfg = 0x70073200ul, 104 .sdrfc = 0x00000C34ul, 105 }; 106 107 static struct ddr3_emif_config ddr3_1066_2g = { 108 .sdcfg = 0x62005662ul, 109 .sdtim1 = 0x0E4C6843ul, 110 .sdtim2 = 0x00001CC6ul, 111 .sdtim3 = 0x323DFF32ul, 112 .sdtim4 = 0x533F08AFul, 113 .zqcfg = 0x70073200ul, 114 .sdrfc = 0x00001044ul, 115 }; 116 117 /* K2G ICE evm DDR3 Configuration */ 118 static struct ddr3_phy_config ddr3phy_800_512mb = { 119 .pllcr = 0x000DC000ul, 120 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 121 .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), 122 .ptr0 = 0x42C21590ul, 123 .ptr1 = 0xD05612C0ul, 124 .ptr2 = 0, 125 .ptr3 = 0x06C30D40ul, 126 .ptr4 = 0x06413880ul, 127 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 128 .dcr_val = ((1 << 10)), 129 .dtpr0 = 0x550E6644ul, 130 .dtpr1 = 0x32834200ul, 131 .dtpr2 = 0x50022A00ul, 132 .mr0 = 0x00001430ul, 133 .mr1 = 0x00000006ul, 134 .mr2 = 0x00000008ul, 135 .dtcr = 0x710035C7ul, 136 .pgcr2 = 0x00F03D09ul, 137 .zq0cr1 = 0x0001005Dul, 138 .zq1cr1 = 0x0001005Bul, 139 .zq2cr1 = 0x0001005Bul, 140 .pir_v1 = 0x00000033ul, 141 .datx8_2_mask = DXEN_MASK, 142 .datx8_2_val = 0, 143 .datx8_3_mask = DXEN_MASK, 144 .datx8_3_val = 0, 145 .datx8_4_mask = DXEN_MASK, 146 .datx8_4_val = 0, 147 .datx8_5_mask = DXEN_MASK, 148 .datx8_5_val = 0, 149 .datx8_6_mask = DXEN_MASK, 150 .datx8_6_val = 0, 151 .datx8_7_mask = DXEN_MASK, 152 .datx8_7_val = 0, 153 .datx8_8_mask = DXEN_MASK, 154 .datx8_8_val = 0, 155 .pir_v2 = 0x00000F81ul, 156 }; 157 158 static struct ddr3_emif_config ddr3_800_512mb = { 159 .sdcfg = 0x62006662ul, 160 .sdtim1 = 0x0A385033ul, 161 .sdtim2 = 0x00001CA5ul, 162 .sdtim3 = 0x21ADFF32ul, 163 .sdtim4 = 0x533F067Ful, 164 .zqcfg = 0x70073200ul, 165 .sdrfc = 0x00000C34ul, 166 }; 167 168 u32 ddr3_init(void) 169 { 170 /* Reset DDR3 PHY after PLL enabled */ 171 ddr3_reset_ddrphy(); 172 if (board_is_k2g_g1()) { 173 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g); 174 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g); 175 } else if (board_is_k2g_gp()) { 176 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); 177 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); 178 } else if (board_is_k2g_ice()) { 179 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb); 180 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb); 181 } 182 183 return 0; 184 } 185 186 inline int ddr3_get_size(void) 187 { 188 return 2; 189 } 190