1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Keystone2: DDR3 configuration 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #include <common.h> 10 11 #include <asm/arch/ddr3.h> 12 #include "ddr3_cfg.h" 13 14 struct ddr3_phy_config ddr3phy_1600_2g = { 15 .pllcr = 0x0001C000ul, 16 .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 17 .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), 18 .ptr0 = 0x42C21590ul, 19 .ptr1 = 0xD05612C0ul, 20 .ptr2 = 0, /* not set in gel */ 21 .ptr3 = 0x0D861A80ul, 22 .ptr4 = 0x0C827100ul, 23 .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 24 .dcr_val = ((1 << 10)), 25 .dtpr0 = 0x9D5CBB66ul, 26 .dtpr1 = 0x12868300ul, 27 .dtpr2 = 0x5002D200ul, 28 .mr0 = 0x00001C70ul, 29 .mr1 = 0x00000006ul, 30 .mr2 = 0x00000018ul, 31 .dtcr = 0x710035C7ul, 32 .pgcr2 = 0x00F07A12ul, 33 .zq0cr1 = 0x0001005Dul, 34 .zq1cr1 = 0x0001005Bul, 35 .zq2cr1 = 0x0001005Bul, 36 .pir_v1 = 0x00000033ul, 37 .pir_v2 = 0x0000FF81ul, 38 }; 39 40 struct ddr3_emif_config ddr3_1600_2g = { 41 .sdcfg = 0x6200CE62ul, 42 .sdtim1 = 0x166C9855ul, 43 .sdtim2 = 0x00001D4Aul, 44 .sdtim3 = 0x435DFF53ul, 45 .sdtim4 = 0x543F0CFFul, 46 .zqcfg = 0x70073200ul, 47 .sdrfc = 0x00001869ul, 48 }; 49