xref: /openbmc/u-boot/board/ti/ks2_evm/ddr3_cfg.c (revision 214cc905defa58b2beb57033ebc6e66a2a90d769)
1  /*
2   * Keystone2: DDR3 configuration
3   *
4   * (C) Copyright 2012-2014
5   *     Texas Instruments Incorporated, <www.ti.com>
6   *
7   * SPDX-License-Identifier:     GPL-2.0+
8   */
9  
10  #include <common.h>
11  
12  #include <asm/arch/ddr3.h>
13  #include "ddr3_cfg.h"
14  
15  struct ddr3_phy_config ddr3phy_1600_2g = {
16  	.pllcr          = 0x0001C000ul,
17  	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
18  	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
19  	.ptr0           = 0x42C21590ul,
20  	.ptr1           = 0xD05612C0ul,
21  	.ptr2           = 0, /* not set in gel */
22  	.ptr3           = 0x0D861A80ul,
23  	.ptr4           = 0x0C827100ul,
24  	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
25  	.dcr_val        = ((1 << 10)),
26  	.dtpr0          = 0x9D5CBB66ul,
27  	.dtpr1          = 0x12868300ul,
28  	.dtpr2          = 0x5002D200ul,
29  	.mr0            = 0x00001C70ul,
30  	.mr1            = 0x00000006ul,
31  	.mr2            = 0x00000018ul,
32  	.dtcr           = 0x710035C7ul,
33  	.pgcr2          = 0x00F07A12ul,
34  	.zq0cr1         = 0x0001005Dul,
35  	.zq1cr1         = 0x0001005Bul,
36  	.zq2cr1         = 0x0001005Bul,
37  	.pir_v1         = 0x00000033ul,
38  	.pir_v2         = 0x0000FF81ul,
39  };
40  
41  struct ddr3_emif_config ddr3_1600_2g = {
42  	.sdcfg          = 0x6200CE62ul,
43  	.sdtim1         = 0x166C9855ul,
44  	.sdtim2         = 0x00001D4Aul,
45  	.sdtim3         = 0x435DFF53ul,
46  	.sdtim4         = 0x543F0CFFul,
47  	.zqcfg          = 0x70073200ul,
48  	.sdrfc          = 0x00001869ul,
49  };
50