1b1babef8SHao Zhang /* 2b1babef8SHao Zhang * Keystone2: DDR3 configuration 3b1babef8SHao Zhang * 4b1babef8SHao Zhang * (C) Copyright 2012-2014 5b1babef8SHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6b1babef8SHao Zhang * 7b1babef8SHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8b1babef8SHao Zhang */ 9b1babef8SHao Zhang 10b1babef8SHao Zhang #include <common.h> 11b1babef8SHao Zhang 12b1babef8SHao Zhang #include <asm/arch/ddr3.h> 13*d9a76e77SVitaly Andrianov #include "ddr3_cfg.h" 14a9068479SHao Zhang 15345af534SHao Zhang struct ddr3_phy_config ddr3phy_1600_2g = { 16345af534SHao Zhang .pllcr = 0x0001C000ul, 17345af534SHao Zhang .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), 18345af534SHao Zhang .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), 19345af534SHao Zhang .ptr0 = 0x42C21590ul, 20345af534SHao Zhang .ptr1 = 0xD05612C0ul, 21345af534SHao Zhang .ptr2 = 0, /* not set in gel */ 22345af534SHao Zhang .ptr3 = 0x0D861A80ul, 23345af534SHao Zhang .ptr4 = 0x0C827100ul, 24345af534SHao Zhang .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), 25345af534SHao Zhang .dcr_val = ((1 << 10)), 26345af534SHao Zhang .dtpr0 = 0x9D5CBB66ul, 27345af534SHao Zhang .dtpr1 = 0x12868300ul, 28345af534SHao Zhang .dtpr2 = 0x5002D200ul, 29345af534SHao Zhang .mr0 = 0x00001C70ul, 30345af534SHao Zhang .mr1 = 0x00000006ul, 31345af534SHao Zhang .mr2 = 0x00000018ul, 32345af534SHao Zhang .dtcr = 0x710035C7ul, 33345af534SHao Zhang .pgcr2 = 0x00F07A12ul, 34345af534SHao Zhang .zq0cr1 = 0x0001005Dul, 35345af534SHao Zhang .zq1cr1 = 0x0001005Bul, 36345af534SHao Zhang .zq2cr1 = 0x0001005Bul, 37345af534SHao Zhang .pir_v1 = 0x00000033ul, 38345af534SHao Zhang .pir_v2 = 0x0000FF81ul, 39345af534SHao Zhang }; 40345af534SHao Zhang 41345af534SHao Zhang struct ddr3_emif_config ddr3_1600_2g = { 42345af534SHao Zhang .sdcfg = 0x6200CE62ul, 43345af534SHao Zhang .sdtim1 = 0x166C9855ul, 44345af534SHao Zhang .sdtim2 = 0x00001D4Aul, 45345af534SHao Zhang .sdtim3 = 0x435DFF53ul, 46345af534SHao Zhang .sdtim4 = 0x543F0CFFul, 47345af534SHao Zhang .zqcfg = 0x70073200ul, 48345af534SHao Zhang .sdrfc = 0x00001869ul, 49345af534SHao Zhang }; 50