1 /* 2 * K2L EVM : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/ddr3.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/ti-common/keystone_net.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 unsigned int get_external_clk(u32 clk) 18 { 19 unsigned int clk_freq; 20 21 switch (clk) { 22 case sys_clk: 23 clk_freq = 122880000; 24 break; 25 case alt_core_clk: 26 clk_freq = 100000000; 27 break; 28 case pa_clk: 29 clk_freq = 122880000; 30 break; 31 case tetris_clk: 32 clk_freq = 122880000; 33 break; 34 case ddr3a_clk: 35 clk_freq = 100000000; 36 break; 37 default: 38 clk_freq = 0; 39 break; 40 } 41 42 return clk_freq; 43 } 44 45 static struct pll_init_data core_pll_config[NUM_SPDS] = { 46 [SPD800] = CORE_PLL_799, 47 [SPD1000] = CORE_PLL_1000, 48 [SPD1200] = CORE_PLL_1198, 49 }; 50 51 s16 divn_val[16] = { 52 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 53 }; 54 55 static struct pll_init_data tetris_pll_config[] = { 56 [SPD800] = TETRIS_PLL_799, 57 [SPD1000] = TETRIS_PLL_1000, 58 [SPD1200] = TETRIS_PLL_1198, 59 [SPD1350] = TETRIS_PLL_1352, 60 [SPD1400] = TETRIS_PLL_1401, 61 }; 62 63 static struct pll_init_data pa_pll_config = 64 PASS_PLL_983; 65 66 struct pll_init_data *get_pll_init_data(int pll) 67 { 68 int speed; 69 struct pll_init_data *data; 70 71 switch (pll) { 72 case MAIN_PLL: 73 speed = get_max_dev_speed(speeds); 74 data = &core_pll_config[speed]; 75 break; 76 case TETRIS_PLL: 77 speed = get_max_arm_speed(speeds); 78 data = &tetris_pll_config[speed]; 79 break; 80 case PASS_PLL: 81 data = &pa_pll_config; 82 break; 83 default: 84 data = NULL; 85 } 86 87 return data; 88 } 89 90 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 91 struct eth_priv_t eth_priv_cfg[] = { 92 { 93 .int_name = "K2L_EMAC", 94 .rx_flow = 0, 95 .phy_addr = 0, 96 .slave_port = 1, 97 .sgmii_link_type = SGMII_LINK_MAC_PHY, 98 .phy_if = PHY_INTERFACE_MODE_SGMII, 99 }, 100 { 101 .int_name = "K2L_EMAC1", 102 .rx_flow = 8, 103 .phy_addr = 1, 104 .slave_port = 2, 105 .sgmii_link_type = SGMII_LINK_MAC_PHY, 106 .phy_if = PHY_INTERFACE_MODE_SGMII, 107 }, 108 { 109 .int_name = "K2L_EMAC2", 110 .rx_flow = 16, 111 .phy_addr = 2, 112 .slave_port = 3, 113 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 114 .phy_if = PHY_INTERFACE_MODE_SGMII, 115 }, 116 { 117 .int_name = "K2L_EMAC3", 118 .rx_flow = 32, 119 .phy_addr = 3, 120 .slave_port = 4, 121 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 122 .phy_if = PHY_INTERFACE_MODE_SGMII, 123 }, 124 }; 125 126 int get_num_eth_ports(void) 127 { 128 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 129 } 130 #endif 131 132 #ifdef CONFIG_BOARD_EARLY_INIT_F 133 int board_early_init_f(void) 134 { 135 init_plls(); 136 137 return 0; 138 } 139 #endif 140 141 #if defined(CONFIG_FIT_EMBED) 142 int board_fit_config_name_match(const char *name) 143 { 144 if (!strcmp(name, "keystone-k2l-evm")) 145 return 0; 146 147 return -1; 148 } 149 #endif 150 151 #ifdef CONFIG_SPL_BUILD 152 void spl_init_keystone_plls(void) 153 { 154 init_plls(); 155 } 156 #endif 157