1345af534SHao Zhang /* 2345af534SHao Zhang * K2L EVM : Board initialization 3345af534SHao Zhang * 4345af534SHao Zhang * (C) Copyright 2014 5345af534SHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6345af534SHao Zhang * 7345af534SHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8345af534SHao Zhang */ 9345af534SHao Zhang 10345af534SHao Zhang #include <common.h> 11345af534SHao Zhang #include <asm/arch/ddr3.h> 12345af534SHao Zhang #include <asm/arch/hardware.h> 13796bcee6SHao Zhang #include <asm/ti-common/keystone_net.h> 14345af534SHao Zhang 15345af534SHao Zhang DECLARE_GLOBAL_DATA_PTR; 16345af534SHao Zhang 17*ee3c6532SLokesh Vutla unsigned int get_external_clk(u32 clk) 18*ee3c6532SLokesh Vutla { 19*ee3c6532SLokesh Vutla unsigned int clk_freq; 20*ee3c6532SLokesh Vutla 21*ee3c6532SLokesh Vutla switch (clk) { 22*ee3c6532SLokesh Vutla case sys_clk: 23*ee3c6532SLokesh Vutla clk_freq = 122880000; 24*ee3c6532SLokesh Vutla break; 25*ee3c6532SLokesh Vutla case alt_core_clk: 26*ee3c6532SLokesh Vutla clk_freq = 100000000; 27*ee3c6532SLokesh Vutla break; 28*ee3c6532SLokesh Vutla case pa_clk: 29*ee3c6532SLokesh Vutla clk_freq = 122880000; 30*ee3c6532SLokesh Vutla break; 31*ee3c6532SLokesh Vutla case tetris_clk: 32*ee3c6532SLokesh Vutla clk_freq = 122880000; 33*ee3c6532SLokesh Vutla break; 34*ee3c6532SLokesh Vutla case ddr3a_clk: 35*ee3c6532SLokesh Vutla clk_freq = 100000000; 36*ee3c6532SLokesh Vutla break; 37*ee3c6532SLokesh Vutla default: 38*ee3c6532SLokesh Vutla clk_freq = 0; 39*ee3c6532SLokesh Vutla break; 40*ee3c6532SLokesh Vutla } 41*ee3c6532SLokesh Vutla 42*ee3c6532SLokesh Vutla return clk_freq; 43*ee3c6532SLokesh Vutla } 44345af534SHao Zhang 457b50e159SLokesh Vutla static struct pll_init_data core_pll_config[NUM_SPDS] = { 467b50e159SLokesh Vutla [SPD800] = CORE_PLL_799, 477b50e159SLokesh Vutla [SPD1000] = CORE_PLL_1000, 4876b3f195SLokesh Vutla [SPD1200] = CORE_PLL_1198, 49345af534SHao Zhang }; 50345af534SHao Zhang 51c321a236SLokesh Vutla s16 divn_val[16] = { 52c321a236SLokesh Vutla 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 53c321a236SLokesh Vutla }; 54c321a236SLokesh Vutla 55345af534SHao Zhang static struct pll_init_data tetris_pll_config[] = { 567b50e159SLokesh Vutla [SPD800] = TETRIS_PLL_799, 577b50e159SLokesh Vutla [SPD1000] = TETRIS_PLL_1000, 587b50e159SLokesh Vutla [SPD1200] = TETRIS_PLL_1198, 597b50e159SLokesh Vutla [SPD1350] = TETRIS_PLL_1352, 607b50e159SLokesh Vutla [SPD1400] = TETRIS_PLL_1401, 61345af534SHao Zhang }; 62345af534SHao Zhang 63345af534SHao Zhang static struct pll_init_data pa_pll_config = 64345af534SHao Zhang PASS_PLL_983; 65345af534SHao Zhang 6694069301SLokesh Vutla struct pll_init_data *get_pll_init_data(int pll) 6794069301SLokesh Vutla { 6894069301SLokesh Vutla int speed; 6994069301SLokesh Vutla struct pll_init_data *data; 7094069301SLokesh Vutla 7194069301SLokesh Vutla switch (pll) { 7294069301SLokesh Vutla case MAIN_PLL: 735cd1f6bdSLokesh Vutla speed = get_max_dev_speed(speeds); 7494069301SLokesh Vutla data = &core_pll_config[speed]; 7594069301SLokesh Vutla break; 7694069301SLokesh Vutla case TETRIS_PLL: 775cd1f6bdSLokesh Vutla speed = get_max_arm_speed(speeds); 7894069301SLokesh Vutla data = &tetris_pll_config[speed]; 7994069301SLokesh Vutla break; 8094069301SLokesh Vutla case PASS_PLL: 8194069301SLokesh Vutla data = &pa_pll_config; 8294069301SLokesh Vutla break; 8394069301SLokesh Vutla default: 8494069301SLokesh Vutla data = NULL; 8594069301SLokesh Vutla } 8694069301SLokesh Vutla 8794069301SLokesh Vutla return data; 8894069301SLokesh Vutla } 8994069301SLokesh Vutla 90796bcee6SHao Zhang #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 91796bcee6SHao Zhang struct eth_priv_t eth_priv_cfg[] = { 92796bcee6SHao Zhang { 93796bcee6SHao Zhang .int_name = "K2L_EMAC", 94796bcee6SHao Zhang .rx_flow = 0, 95796bcee6SHao Zhang .phy_addr = 0, 96796bcee6SHao Zhang .slave_port = 1, 97796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_PHY, 98bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 99796bcee6SHao Zhang }, 100796bcee6SHao Zhang { 101796bcee6SHao Zhang .int_name = "K2L_EMAC1", 102796bcee6SHao Zhang .rx_flow = 8, 103796bcee6SHao Zhang .phy_addr = 1, 104796bcee6SHao Zhang .slave_port = 2, 105796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_PHY, 106bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 107796bcee6SHao Zhang }, 108796bcee6SHao Zhang { 109796bcee6SHao Zhang .int_name = "K2L_EMAC2", 110796bcee6SHao Zhang .rx_flow = 16, 111796bcee6SHao Zhang .phy_addr = 2, 112796bcee6SHao Zhang .slave_port = 3, 113796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 114bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 115796bcee6SHao Zhang }, 116796bcee6SHao Zhang { 117796bcee6SHao Zhang .int_name = "K2L_EMAC3", 118796bcee6SHao Zhang .rx_flow = 32, 119796bcee6SHao Zhang .phy_addr = 3, 120796bcee6SHao Zhang .slave_port = 4, 121796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 122bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 123796bcee6SHao Zhang }, 124796bcee6SHao Zhang }; 125796bcee6SHao Zhang 126796bcee6SHao Zhang int get_num_eth_ports(void) 127796bcee6SHao Zhang { 128796bcee6SHao Zhang return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 129796bcee6SHao Zhang } 130796bcee6SHao Zhang #endif 131796bcee6SHao Zhang 132345af534SHao Zhang #ifdef CONFIG_BOARD_EARLY_INIT_F 133345af534SHao Zhang int board_early_init_f(void) 134345af534SHao Zhang { 13594069301SLokesh Vutla init_plls(); 136345af534SHao Zhang 137345af534SHao Zhang return 0; 138345af534SHao Zhang } 139345af534SHao Zhang #endif 140345af534SHao Zhang 141345af534SHao Zhang #ifdef CONFIG_SPL_BUILD 142345af534SHao Zhang void spl_init_keystone_plls(void) 143345af534SHao Zhang { 14494069301SLokesh Vutla init_plls(); 145345af534SHao Zhang } 146345af534SHao Zhang #endif 147