1345af534SHao Zhang /* 2345af534SHao Zhang * K2L EVM : Board initialization 3345af534SHao Zhang * 4345af534SHao Zhang * (C) Copyright 2014 5345af534SHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6345af534SHao Zhang * 7345af534SHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8345af534SHao Zhang */ 9345af534SHao Zhang 10345af534SHao Zhang #include <common.h> 11345af534SHao Zhang #include <asm/arch/ddr3.h> 12345af534SHao Zhang #include <asm/arch/hardware.h> 13796bcee6SHao Zhang #include <asm/ti-common/keystone_net.h> 14345af534SHao Zhang 15345af534SHao Zhang DECLARE_GLOBAL_DATA_PTR; 16345af534SHao Zhang 17345af534SHao Zhang unsigned int external_clk[ext_clk_count] = { 18345af534SHao Zhang [sys_clk] = 122880000, 19345af534SHao Zhang [alt_core_clk] = 100000000, 20345af534SHao Zhang [pa_clk] = 122880000, 21345af534SHao Zhang [tetris_clk] = 122880000, 227531122eSLokesh Vutla [ddr3a_clk] = 100000000, 23345af534SHao Zhang }; 24345af534SHao Zhang 257b50e159SLokesh Vutla static struct pll_init_data core_pll_config[NUM_SPDS] = { 267b50e159SLokesh Vutla [SPD800] = CORE_PLL_799, 277b50e159SLokesh Vutla [SPD1000] = CORE_PLL_1000, 2876b3f195SLokesh Vutla [SPD1200] = CORE_PLL_1198, 29345af534SHao Zhang }; 30345af534SHao Zhang 31c321a236SLokesh Vutla s16 divn_val[16] = { 32c321a236SLokesh Vutla 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 33c321a236SLokesh Vutla }; 34c321a236SLokesh Vutla 35345af534SHao Zhang static struct pll_init_data tetris_pll_config[] = { 367b50e159SLokesh Vutla [SPD800] = TETRIS_PLL_799, 377b50e159SLokesh Vutla [SPD1000] = TETRIS_PLL_1000, 387b50e159SLokesh Vutla [SPD1200] = TETRIS_PLL_1198, 397b50e159SLokesh Vutla [SPD1350] = TETRIS_PLL_1352, 407b50e159SLokesh Vutla [SPD1400] = TETRIS_PLL_1401, 41345af534SHao Zhang }; 42345af534SHao Zhang 43345af534SHao Zhang static struct pll_init_data pa_pll_config = 44345af534SHao Zhang PASS_PLL_983; 45345af534SHao Zhang 4694069301SLokesh Vutla struct pll_init_data *get_pll_init_data(int pll) 4794069301SLokesh Vutla { 4894069301SLokesh Vutla int speed; 4994069301SLokesh Vutla struct pll_init_data *data; 5094069301SLokesh Vutla 5194069301SLokesh Vutla switch (pll) { 5294069301SLokesh Vutla case MAIN_PLL: 5394069301SLokesh Vutla speed = get_max_dev_speed(); 5494069301SLokesh Vutla data = &core_pll_config[speed]; 5594069301SLokesh Vutla break; 5694069301SLokesh Vutla case TETRIS_PLL: 5794069301SLokesh Vutla speed = get_max_arm_speed(); 5894069301SLokesh Vutla data = &tetris_pll_config[speed]; 5994069301SLokesh Vutla break; 6094069301SLokesh Vutla case PASS_PLL: 6194069301SLokesh Vutla data = &pa_pll_config; 6294069301SLokesh Vutla break; 6394069301SLokesh Vutla default: 6494069301SLokesh Vutla data = NULL; 6594069301SLokesh Vutla } 6694069301SLokesh Vutla 6794069301SLokesh Vutla return data; 6894069301SLokesh Vutla } 6994069301SLokesh Vutla 70796bcee6SHao Zhang #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 71796bcee6SHao Zhang struct eth_priv_t eth_priv_cfg[] = { 72796bcee6SHao Zhang { 73796bcee6SHao Zhang .int_name = "K2L_EMAC", 74796bcee6SHao Zhang .rx_flow = 0, 75796bcee6SHao Zhang .phy_addr = 0, 76796bcee6SHao Zhang .slave_port = 1, 77796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_PHY, 78*bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 79796bcee6SHao Zhang }, 80796bcee6SHao Zhang { 81796bcee6SHao Zhang .int_name = "K2L_EMAC1", 82796bcee6SHao Zhang .rx_flow = 8, 83796bcee6SHao Zhang .phy_addr = 1, 84796bcee6SHao Zhang .slave_port = 2, 85796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_PHY, 86*bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 87796bcee6SHao Zhang }, 88796bcee6SHao Zhang { 89796bcee6SHao Zhang .int_name = "K2L_EMAC2", 90796bcee6SHao Zhang .rx_flow = 16, 91796bcee6SHao Zhang .phy_addr = 2, 92796bcee6SHao Zhang .slave_port = 3, 93796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 94*bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 95796bcee6SHao Zhang }, 96796bcee6SHao Zhang { 97796bcee6SHao Zhang .int_name = "K2L_EMAC3", 98796bcee6SHao Zhang .rx_flow = 32, 99796bcee6SHao Zhang .phy_addr = 3, 100796bcee6SHao Zhang .slave_port = 4, 101796bcee6SHao Zhang .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 102*bf7bd4e7SMugunthan V N .phy_if = PHY_INTERFACE_MODE_SGMII, 103796bcee6SHao Zhang }, 104796bcee6SHao Zhang }; 105796bcee6SHao Zhang 106796bcee6SHao Zhang int get_num_eth_ports(void) 107796bcee6SHao Zhang { 108796bcee6SHao Zhang return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 109796bcee6SHao Zhang } 110796bcee6SHao Zhang #endif 111796bcee6SHao Zhang 112345af534SHao Zhang #ifdef CONFIG_BOARD_EARLY_INIT_F 113345af534SHao Zhang int board_early_init_f(void) 114345af534SHao Zhang { 11594069301SLokesh Vutla init_plls(); 116345af534SHao Zhang 117345af534SHao Zhang return 0; 118345af534SHao Zhang } 119345af534SHao Zhang #endif 120345af534SHao Zhang 121345af534SHao Zhang #ifdef CONFIG_SPL_BUILD 122345af534SHao Zhang void spl_init_keystone_plls(void) 123345af534SHao Zhang { 12494069301SLokesh Vutla init_plls(); 125345af534SHao Zhang } 126345af534SHao Zhang #endif 127