1 /* 2 * K2G EVM : Board initialization 3 * 4 * (C) Copyright 2015 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 #include <asm/ti-common/keystone_net.h> 12 #include <asm/arch/psc_defs.h> 13 #include <asm/arch/mmc_host_def.h> 14 #include <fdtdec.h> 15 #include <i2c.h> 16 #include <remoteproc.h> 17 #include "mux-k2g.h" 18 #include "../common/board_detect.h" 19 20 #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B 21 22 const unsigned int sysclk_array[MAX_SYSCLK] = { 23 19200000, 24 24000000, 25 25000000, 26 26000000, 27 }; 28 29 unsigned int get_external_clk(u32 clk) 30 { 31 unsigned int clk_freq; 32 u8 sysclk_index = get_sysclk_index(); 33 34 switch (clk) { 35 case sys_clk: 36 clk_freq = sysclk_array[sysclk_index]; 37 break; 38 case pa_clk: 39 clk_freq = sysclk_array[sysclk_index]; 40 break; 41 case tetris_clk: 42 clk_freq = sysclk_array[sysclk_index]; 43 break; 44 case ddr3a_clk: 45 clk_freq = sysclk_array[sysclk_index]; 46 break; 47 case uart_clk: 48 clk_freq = sysclk_array[sysclk_index]; 49 break; 50 default: 51 clk_freq = 0; 52 break; 53 } 54 55 return clk_freq; 56 } 57 58 int speeds[DEVSPEED_NUMSPDS] = { 59 SPD400, 60 SPD600, 61 SPD800, 62 SPD900, 63 SPD1000, 64 SPD900, 65 SPD800, 66 SPD600, 67 SPD400, 68 SPD200, 69 }; 70 71 static int dev_speeds[DEVSPEED_NUMSPDS] = { 72 SPD600, 73 SPD800, 74 SPD900, 75 SPD1000, 76 SPD900, 77 SPD800, 78 SPD600, 79 SPD400, 80 }; 81 82 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = { 83 [SYSCLK_19MHz] = { 84 [SPD400] = {MAIN_PLL, 125, 3, 2}, 85 [SPD600] = {MAIN_PLL, 125, 2, 2}, 86 [SPD800] = {MAIN_PLL, 250, 3, 2}, 87 [SPD900] = {MAIN_PLL, 187, 2, 2}, 88 [SPD1000] = {MAIN_PLL, 104, 1, 2}, 89 }, 90 [SYSCLK_24MHz] = { 91 [SPD400] = {MAIN_PLL, 100, 3, 2}, 92 [SPD600] = {MAIN_PLL, 300, 6, 2}, 93 [SPD800] = {MAIN_PLL, 200, 3, 2}, 94 [SPD900] = {MAIN_PLL, 75, 1, 2}, 95 [SPD1000] = {MAIN_PLL, 250, 3, 2}, 96 }, 97 [SYSCLK_25MHz] = { 98 [SPD400] = {MAIN_PLL, 32, 1, 2}, 99 [SPD600] = {MAIN_PLL, 48, 1, 2}, 100 [SPD800] = {MAIN_PLL, 64, 1, 2}, 101 [SPD900] = {MAIN_PLL, 72, 1, 2}, 102 [SPD1000] = {MAIN_PLL, 80, 1, 2}, 103 }, 104 [SYSCLK_26MHz] = { 105 [SPD400] = {MAIN_PLL, 400, 13, 2}, 106 [SPD600] = {MAIN_PLL, 230, 5, 2}, 107 [SPD800] = {MAIN_PLL, 123, 2, 2}, 108 [SPD900] = {MAIN_PLL, 69, 1, 2}, 109 [SPD1000] = {MAIN_PLL, 384, 5, 2}, 110 }, 111 }; 112 113 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = { 114 [SYSCLK_19MHz] = { 115 [SPD200] = {TETRIS_PLL, 625, 6, 10}, 116 [SPD400] = {TETRIS_PLL, 125, 1, 6}, 117 [SPD600] = {TETRIS_PLL, 125, 1, 4}, 118 [SPD800] = {TETRIS_PLL, 333, 2, 4}, 119 [SPD900] = {TETRIS_PLL, 187, 2, 2}, 120 [SPD1000] = {TETRIS_PLL, 104, 1, 2}, 121 }, 122 [SYSCLK_24MHz] = { 123 [SPD200] = {TETRIS_PLL, 250, 3, 10}, 124 [SPD400] = {TETRIS_PLL, 100, 1, 6}, 125 [SPD600] = {TETRIS_PLL, 100, 1, 4}, 126 [SPD800] = {TETRIS_PLL, 400, 3, 4}, 127 [SPD900] = {TETRIS_PLL, 75, 1, 2}, 128 [SPD1000] = {TETRIS_PLL, 250, 3, 2}, 129 }, 130 [SYSCLK_25MHz] = { 131 [SPD200] = {TETRIS_PLL, 80, 1, 10}, 132 [SPD400] = {TETRIS_PLL, 96, 1, 6}, 133 [SPD600] = {TETRIS_PLL, 96, 1, 4}, 134 [SPD800] = {TETRIS_PLL, 128, 1, 4}, 135 [SPD900] = {TETRIS_PLL, 72, 1, 2}, 136 [SPD1000] = {TETRIS_PLL, 80, 1, 2}, 137 }, 138 [SYSCLK_26MHz] = { 139 [SPD200] = {TETRIS_PLL, 307, 4, 10}, 140 [SPD400] = {TETRIS_PLL, 369, 4, 6}, 141 [SPD600] = {TETRIS_PLL, 369, 4, 4}, 142 [SPD800] = {TETRIS_PLL, 123, 1, 4}, 143 [SPD900] = {TETRIS_PLL, 69, 1, 2}, 144 [SPD1000] = {TETRIS_PLL, 384, 5, 2}, 145 }, 146 }; 147 148 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = { 149 [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8}, 150 [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8}, 151 [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10}, 152 [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2}, 153 }; 154 155 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = { 156 [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2}, 157 [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2}, 158 [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2}, 159 [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2}, 160 }; 161 162 static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = { 163 [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16}, 164 [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16}, 165 [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16}, 166 [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16}, 167 }; 168 169 static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = { 170 [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14}, 171 [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14}, 172 [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14}, 173 [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14}, 174 }; 175 176 struct pll_init_data *get_pll_init_data(int pll) 177 { 178 int speed; 179 struct pll_init_data *data = NULL; 180 u8 sysclk_index = get_sysclk_index(); 181 182 switch (pll) { 183 case MAIN_PLL: 184 speed = get_max_dev_speed(dev_speeds); 185 data = &main_pll_config[sysclk_index][speed]; 186 break; 187 case TETRIS_PLL: 188 speed = get_max_arm_speed(speeds); 189 data = &tetris_pll_config[sysclk_index][speed]; 190 break; 191 case NSS_PLL: 192 data = &nss_pll_config[sysclk_index]; 193 break; 194 case UART_PLL: 195 data = &uart_pll_config[sysclk_index]; 196 break; 197 case DDR3_PLL: 198 if (cpu_revision() & CPU_66AK2G1x) { 199 speed = get_max_arm_speed(speeds); 200 if (speed == SPD1000) 201 data = &ddr3_pll_config_1066[sysclk_index]; 202 else 203 data = &ddr3_pll_config_800[sysclk_index]; 204 } else { 205 data = &ddr3_pll_config_800[sysclk_index]; 206 } 207 break; 208 default: 209 data = NULL; 210 } 211 212 return data; 213 } 214 215 s16 divn_val[16] = { 216 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 217 }; 218 219 #if defined(CONFIG_MMC) 220 int board_mmc_init(bd_t *bis) 221 { 222 if (psc_enable_module(KS2_LPSC_MMC)) { 223 printf("%s module enabled failed\n", __func__); 224 return -1; 225 } 226 227 if (board_is_k2g_gp() || board_is_k2g_g1()) 228 omap_mmc_init(0, 0, 0, -1, -1); 229 230 omap_mmc_init(1, 0, 0, -1, -1); 231 return 0; 232 } 233 #endif 234 235 #if defined(CONFIG_MULTI_DTB_FIT) 236 int board_fit_config_name_match(const char *name) 237 { 238 bool eeprom_read = board_ti_was_eeprom_read(); 239 240 if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read) 241 return 0; 242 else if (!strcmp(name, "keystone-k2g-evm") && 243 (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1"))) 244 return 0; 245 else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC")) 246 return 0; 247 else 248 return -1; 249 } 250 #endif 251 252 #if defined(CONFIG_DTB_RESELECT) 253 static int k2g_alt_board_detect(void) 254 { 255 int rc; 256 257 rc = i2c_set_bus_num(1); 258 if (rc) 259 return rc; 260 261 rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS); 262 if (rc) 263 return rc; 264 265 ti_i2c_eeprom_am_set("66AK2GGP", "1.0X"); 266 267 return 0; 268 } 269 270 static void k2g_reset_mux_config(void) 271 { 272 /* Unlock the reset mux register */ 273 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); 274 275 /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */ 276 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK, 277 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT); 278 279 /* lock the reset mux register to prevent any spurious writes. */ 280 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); 281 } 282 283 int embedded_dtb_select(void) 284 { 285 int rc; 286 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 287 CONFIG_EEPROM_CHIP_ADDRESS); 288 if (rc) { 289 rc = k2g_alt_board_detect(); 290 if (rc) { 291 printf("Unable to do board detection\n"); 292 return -1; 293 } 294 } 295 296 fdtdec_setup(); 297 298 k2g_mux_config(); 299 300 k2g_reset_mux_config(); 301 302 if (board_is_k2g_gp() || board_is_k2g_g1()) { 303 /* deassert FLASH_HOLD */ 304 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, 305 BIT(9)); 306 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, 307 BIT(9)); 308 } 309 310 return 0; 311 } 312 #endif 313 314 #ifdef CONFIG_BOARD_LATE_INIT 315 int board_late_init(void) 316 { 317 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT) 318 int rc; 319 320 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 321 CONFIG_EEPROM_CHIP_ADDRESS); 322 if (rc) 323 printf("ti_i2c_eeprom_init failed %d\n", rc); 324 325 board_ti_set_ethaddr(1); 326 #endif 327 328 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 329 if (board_is_k2g_gp()) 330 env_set("board_name", "66AK2GGP\0"); 331 else if (board_is_k2g_g1()) 332 env_set("board_name", "66AK2GG1\0"); 333 else if (board_is_k2g_ice()) 334 env_set("board_name", "66AK2GIC\0"); 335 #endif 336 return 0; 337 } 338 #endif 339 340 #ifdef CONFIG_BOARD_EARLY_INIT_F 341 int board_early_init_f(void) 342 { 343 init_plls(); 344 345 k2g_mux_config(); 346 347 return 0; 348 } 349 #endif 350 351 #ifdef CONFIG_SPL_BUILD 352 void spl_init_keystone_plls(void) 353 { 354 init_plls(); 355 } 356 #endif 357 358 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 359 struct eth_priv_t eth_priv_cfg[] = { 360 { 361 .int_name = "K2G_EMAC", 362 .rx_flow = 0, 363 .phy_addr = 0, 364 .slave_port = 1, 365 .sgmii_link_type = SGMII_LINK_MAC_PHY, 366 .phy_if = PHY_INTERFACE_MODE_RGMII, 367 }, 368 }; 369 370 int get_num_eth_ports(void) 371 { 372 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 373 } 374 #endif 375 376 #ifdef CONFIG_TI_SECURE_DEVICE 377 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size) 378 { 379 int id = getenv_ulong("dev_pmmc", 10, 0); 380 int ret; 381 382 if (!rproc_is_initialized()) 383 rproc_init(); 384 385 ret = rproc_load(id, pmmc_image, pmmc_size); 386 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n", 387 id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!"); 388 389 if (!ret) 390 rproc_start(id); 391 } 392 393 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process); 394 #endif 395