1 /* 2 * K2G EVM : Board initialization 3 * 4 * (C) Copyright 2015 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 #include <asm/ti-common/keystone_net.h> 12 #include <asm/arch/psc_defs.h> 13 #include <asm/arch/mmc_host_def.h> 14 #include "mux-k2g.h" 15 #include "../common/board_detect.h" 16 17 const unsigned int sysclk_array[MAX_SYSCLK] = { 18 19200000, 19 24000000, 20 25000000, 21 26000000, 22 }; 23 24 unsigned int get_external_clk(u32 clk) 25 { 26 unsigned int clk_freq; 27 u8 sysclk_index = get_sysclk_index(); 28 29 switch (clk) { 30 case sys_clk: 31 clk_freq = sysclk_array[sysclk_index]; 32 break; 33 case pa_clk: 34 clk_freq = sysclk_array[sysclk_index]; 35 break; 36 case tetris_clk: 37 clk_freq = sysclk_array[sysclk_index]; 38 break; 39 case ddr3a_clk: 40 clk_freq = sysclk_array[sysclk_index]; 41 break; 42 case uart_clk: 43 clk_freq = sysclk_array[sysclk_index]; 44 break; 45 default: 46 clk_freq = 0; 47 break; 48 } 49 50 return clk_freq; 51 } 52 53 static int arm_speeds[DEVSPEED_NUMSPDS] = { 54 SPD400, 55 SPD600, 56 SPD800, 57 SPD900, 58 SPD1000, 59 SPD900, 60 SPD800, 61 SPD600, 62 SPD400, 63 SPD200, 64 }; 65 66 static int dev_speeds[DEVSPEED_NUMSPDS] = { 67 SPD600, 68 SPD800, 69 SPD900, 70 SPD1000, 71 SPD900, 72 SPD800, 73 SPD600, 74 SPD400, 75 }; 76 77 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = { 78 [SYSCLK_19MHz] = { 79 [SPD400] = {MAIN_PLL, 125, 3, 2}, 80 [SPD600] = {MAIN_PLL, 125, 2, 2}, 81 [SPD800] = {MAIN_PLL, 250, 3, 2}, 82 [SPD900] = {MAIN_PLL, 187, 2, 2}, 83 [SPD1000] = {MAIN_PLL, 104, 1, 2}, 84 }, 85 [SYSCLK_24MHz] = { 86 [SPD400] = {MAIN_PLL, 100, 3, 2}, 87 [SPD600] = {MAIN_PLL, 300, 6, 2}, 88 [SPD800] = {MAIN_PLL, 200, 3, 2}, 89 [SPD900] = {MAIN_PLL, 75, 1, 2}, 90 [SPD1000] = {MAIN_PLL, 250, 3, 2}, 91 }, 92 [SYSCLK_25MHz] = { 93 [SPD400] = {MAIN_PLL, 32, 1, 2}, 94 [SPD600] = {MAIN_PLL, 48, 1, 2}, 95 [SPD800] = {MAIN_PLL, 64, 1, 2}, 96 [SPD900] = {MAIN_PLL, 72, 1, 2}, 97 [SPD1000] = {MAIN_PLL, 80, 1, 2}, 98 }, 99 [SYSCLK_26MHz] = { 100 [SPD400] = {MAIN_PLL, 400, 13, 2}, 101 [SPD600] = {MAIN_PLL, 230, 5, 2}, 102 [SPD800] = {MAIN_PLL, 123, 2, 2}, 103 [SPD900] = {MAIN_PLL, 69, 1, 2}, 104 [SPD1000] = {MAIN_PLL, 384, 5, 2}, 105 }, 106 }; 107 108 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = { 109 [SYSCLK_19MHz] = { 110 [SPD200] = {TETRIS_PLL, 625, 6, 10}, 111 [SPD400] = {TETRIS_PLL, 125, 1, 6}, 112 [SPD600] = {TETRIS_PLL, 125, 1, 4}, 113 [SPD800] = {TETRIS_PLL, 333, 2, 4}, 114 [SPD900] = {TETRIS_PLL, 187, 2, 2}, 115 [SPD1000] = {TETRIS_PLL, 104, 1, 2}, 116 }, 117 [SYSCLK_24MHz] = { 118 [SPD200] = {TETRIS_PLL, 250, 3, 10}, 119 [SPD400] = {TETRIS_PLL, 100, 1, 6}, 120 [SPD600] = {TETRIS_PLL, 100, 1, 4}, 121 [SPD800] = {TETRIS_PLL, 400, 3, 4}, 122 [SPD900] = {TETRIS_PLL, 75, 1, 2}, 123 [SPD1000] = {TETRIS_PLL, 250, 3, 2}, 124 }, 125 [SYSCLK_25MHz] = { 126 [SPD200] = {TETRIS_PLL, 80, 1, 10}, 127 [SPD400] = {TETRIS_PLL, 96, 1, 6}, 128 [SPD600] = {TETRIS_PLL, 96, 1, 4}, 129 [SPD800] = {TETRIS_PLL, 128, 1, 4}, 130 [SPD900] = {TETRIS_PLL, 72, 1, 2}, 131 [SPD1000] = {TETRIS_PLL, 80, 1, 2}, 132 }, 133 [SYSCLK_26MHz] = { 134 [SPD200] = {TETRIS_PLL, 307, 4, 10}, 135 [SPD400] = {TETRIS_PLL, 369, 4, 6}, 136 [SPD600] = {TETRIS_PLL, 369, 4, 4}, 137 [SPD800] = {TETRIS_PLL, 123, 1, 4}, 138 [SPD900] = {TETRIS_PLL, 69, 1, 2}, 139 [SPD1000] = {TETRIS_PLL, 384, 5, 2}, 140 }, 141 }; 142 143 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = { 144 [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8}, 145 [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8}, 146 [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10}, 147 [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2}, 148 }; 149 150 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = { 151 [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2}, 152 [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2}, 153 [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2}, 154 [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2}, 155 }; 156 157 static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = { 158 [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16}, 159 [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16}, 160 [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16}, 161 [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16}, 162 }; 163 164 struct pll_init_data *get_pll_init_data(int pll) 165 { 166 int speed; 167 struct pll_init_data *data = NULL; 168 u8 sysclk_index = get_sysclk_index(); 169 170 switch (pll) { 171 case MAIN_PLL: 172 speed = get_max_dev_speed(dev_speeds); 173 data = &main_pll_config[sysclk_index][speed]; 174 break; 175 case TETRIS_PLL: 176 speed = get_max_arm_speed(arm_speeds); 177 data = &tetris_pll_config[sysclk_index][speed]; 178 break; 179 case NSS_PLL: 180 data = &nss_pll_config[sysclk_index]; 181 break; 182 case UART_PLL: 183 data = &uart_pll_config[sysclk_index]; 184 break; 185 case DDR3_PLL: 186 data = &ddr3_pll_config[sysclk_index]; 187 break; 188 default: 189 data = NULL; 190 } 191 192 return data; 193 } 194 195 s16 divn_val[16] = { 196 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 197 }; 198 199 #if defined(CONFIG_MMC) 200 int board_mmc_init(bd_t *bis) 201 { 202 if (psc_enable_module(KS2_LPSC_MMC)) { 203 printf("%s module enabled failed\n", __func__); 204 return -1; 205 } 206 207 omap_mmc_init(0, 0, 0, -1, -1); 208 omap_mmc_init(1, 0, 0, -1, -1); 209 return 0; 210 } 211 #endif 212 213 #ifdef CONFIG_BOARD_EARLY_INIT_F 214 215 static void k2g_reset_mux_config(void) 216 { 217 /* Unlock the reset mux register */ 218 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); 219 220 /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */ 221 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK, 222 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT); 223 224 /* lock the reset mux register to prevent any spurious writes. */ 225 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); 226 } 227 228 int board_early_init_f(void) 229 { 230 init_plls(); 231 232 k2g_mux_config(); 233 234 k2g_reset_mux_config(); 235 236 /* deassert FLASH_HOLD */ 237 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, 238 BIT(9)); 239 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, 240 BIT(9)); 241 242 return 0; 243 } 244 #endif 245 246 #ifdef CONFIG_BOARD_LATE_INIT 247 int board_late_init(void) 248 { 249 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT) 250 int rc; 251 252 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 253 CONFIG_EEPROM_CHIP_ADDRESS); 254 if (rc) 255 printf("ti_i2c_eeprom_init failed %d\n", rc); 256 257 board_ti_set_ethaddr(1); 258 #endif 259 260 return 0; 261 } 262 #endif 263 264 #ifdef CONFIG_SPL_BUILD 265 void spl_init_keystone_plls(void) 266 { 267 init_plls(); 268 } 269 #endif 270 271 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 272 struct eth_priv_t eth_priv_cfg[] = { 273 { 274 .int_name = "K2G_EMAC", 275 .rx_flow = 0, 276 .phy_addr = 0, 277 .slave_port = 1, 278 .sgmii_link_type = SGMII_LINK_MAC_PHY, 279 .phy_if = PHY_INTERFACE_MODE_RGMII, 280 }, 281 }; 282 283 int get_num_eth_ports(void) 284 { 285 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 286 } 287 #endif 288