1 /* 2 * K2G EVM : Board initialization 3 * 4 * (C) Copyright 2015 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 #include <asm/ti-common/keystone_net.h> 12 #include <asm/arch/psc_defs.h> 13 #include <asm/arch/mmc_host_def.h> 14 #include "mux-k2g.h" 15 16 #define SYS_CLK 24000000 17 18 unsigned int external_clk[ext_clk_count] = { 19 [sys_clk] = SYS_CLK, 20 [pa_clk] = SYS_CLK, 21 [tetris_clk] = SYS_CLK, 22 [ddr3a_clk] = SYS_CLK, 23 [uart_clk] = SYS_CLK, 24 }; 25 26 static int arm_speeds[DEVSPEED_NUMSPDS] = { 27 SPD400, 28 SPD600, 29 SPD800, 30 SPD900, 31 SPD1000, 32 SPD900, 33 SPD800, 34 SPD600, 35 SPD400, 36 SPD200, 37 }; 38 39 static int dev_speeds[DEVSPEED_NUMSPDS] = { 40 SPD600, 41 SPD800, 42 SPD900, 43 SPD1000, 44 SPD900, 45 SPD800, 46 SPD600, 47 SPD400, 48 }; 49 50 static struct pll_init_data main_pll_config[NUM_SPDS] = { 51 [SPD400] = {MAIN_PLL, 100, 3, 2}, 52 [SPD600] = {MAIN_PLL, 300, 6, 2}, 53 [SPD800] = {MAIN_PLL, 200, 3, 2}, 54 [SPD900] = {TETRIS_PLL, 75, 1, 2}, 55 [SPD1000] = {TETRIS_PLL, 250, 3, 2}, 56 }; 57 58 static struct pll_init_data tetris_pll_config[NUM_SPDS] = { 59 [SPD200] = {TETRIS_PLL, 250, 3, 10}, 60 [SPD400] = {TETRIS_PLL, 100, 1, 6}, 61 [SPD600] = {TETRIS_PLL, 100, 1, 4}, 62 [SPD800] = {TETRIS_PLL, 400, 3, 4}, 63 [SPD900] = {TETRIS_PLL, 75, 1, 2}, 64 [SPD1000] = {TETRIS_PLL, 250, 3, 2}, 65 }; 66 67 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; 68 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; 69 static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; 70 71 struct pll_init_data *get_pll_init_data(int pll) 72 { 73 int speed; 74 struct pll_init_data *data = NULL; 75 76 switch (pll) { 77 case MAIN_PLL: 78 speed = get_max_dev_speed(dev_speeds); 79 data = &main_pll_config[speed]; 80 break; 81 case TETRIS_PLL: 82 speed = get_max_arm_speed(arm_speeds); 83 data = &tetris_pll_config[speed]; 84 break; 85 case NSS_PLL: 86 data = &nss_pll_config; 87 break; 88 case UART_PLL: 89 data = &uart_pll_config; 90 break; 91 case DDR3_PLL: 92 data = &ddr3_pll_config; 93 break; 94 default: 95 data = NULL; 96 } 97 98 return data; 99 } 100 101 s16 divn_val[16] = { 102 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 103 }; 104 105 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 106 int board_mmc_init(bd_t *bis) 107 { 108 if (psc_enable_module(KS2_LPSC_MMC)) { 109 printf("%s module enabled failed\n", __func__); 110 return -1; 111 } 112 113 omap_mmc_init(0, 0, 0, -1, -1); 114 omap_mmc_init(1, 0, 0, -1, -1); 115 return 0; 116 } 117 #endif 118 119 #ifdef CONFIG_BOARD_EARLY_INIT_F 120 121 static void k2g_reset_mux_config(void) 122 { 123 /* Unlock the reset mux register */ 124 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); 125 126 /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */ 127 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK, 128 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT); 129 130 /* lock the reset mux register to prevent any spurious writes. */ 131 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); 132 } 133 134 int board_early_init_f(void) 135 { 136 init_plls(); 137 138 k2g_mux_config(); 139 140 k2g_reset_mux_config(); 141 142 /* deassert FLASH_HOLD */ 143 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, 144 BIT(9)); 145 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, 146 BIT(9)); 147 148 return 0; 149 } 150 #endif 151 152 #ifdef CONFIG_SPL_BUILD 153 void spl_init_keystone_plls(void) 154 { 155 init_plls(); 156 } 157 #endif 158 159 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 160 struct eth_priv_t eth_priv_cfg[] = { 161 { 162 .int_name = "K2G_EMAC", 163 .rx_flow = 0, 164 .phy_addr = 0, 165 .slave_port = 1, 166 .sgmii_link_type = SGMII_LINK_MAC_PHY, 167 .phy_if = PHY_INTERFACE_MODE_RGMII, 168 }, 169 }; 170 171 int get_num_eth_ports(void) 172 { 173 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 174 } 175 #endif 176