1 /* 2 * K2E EVM : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/ddr3.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/ti-common/keystone_net.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 unsigned int external_clk[ext_clk_count] = { 18 [sys_clk] = 100000000, 19 [alt_core_clk] = 100000000, 20 [pa_clk] = 100000000, 21 [ddr3a_clk] = 100000000, 22 }; 23 24 static struct pll_init_data core_pll_config[NUM_SPDS] = { 25 [SPD800] = CORE_PLL_800, 26 [SPD850] = CORE_PLL_850, 27 [SPD1000] = CORE_PLL_1000, 28 [SPD1250] = CORE_PLL_1250, 29 [SPD1350] = CORE_PLL_1350, 30 [SPD1400] = CORE_PLL_1400, 31 [SPD1500] = CORE_PLL_1500, 32 }; 33 34 /* DEV and ARM speed definitions as specified in DEVSPEED register */ 35 int speeds[DEVSPEED_NUMSPDS] = { 36 SPD850, 37 SPD1000, 38 SPD1250, 39 SPD1350, 40 SPD1400, 41 SPD1500, 42 SPD1400, 43 SPD1350, 44 SPD1250, 45 SPD1000, 46 SPD850, 47 SPD800, 48 }; 49 50 s16 divn_val[16] = { 51 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 52 }; 53 54 static struct pll_init_data pa_pll_config = 55 PASS_PLL_1000; 56 57 struct pll_init_data *get_pll_init_data(int pll) 58 { 59 int speed; 60 struct pll_init_data *data; 61 62 switch (pll) { 63 case MAIN_PLL: 64 speed = get_max_dev_speed(); 65 data = &core_pll_config[speed]; 66 break; 67 case PASS_PLL: 68 data = &pa_pll_config; 69 break; 70 default: 71 data = NULL; 72 } 73 74 return data; 75 } 76 77 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 78 struct eth_priv_t eth_priv_cfg[] = { 79 { 80 .int_name = "K2E_EMAC0", 81 .rx_flow = 0, 82 .phy_addr = 0, 83 .slave_port = 1, 84 .sgmii_link_type = SGMII_LINK_MAC_PHY, 85 .phy_if = PHY_INTERFACE_MODE_SGMII, 86 }, 87 { 88 .int_name = "K2E_EMAC1", 89 .rx_flow = 8, 90 .phy_addr = 1, 91 .slave_port = 2, 92 .sgmii_link_type = SGMII_LINK_MAC_PHY, 93 .phy_if = PHY_INTERFACE_MODE_SGMII, 94 }, 95 { 96 .int_name = "K2E_EMAC2", 97 .rx_flow = 16, 98 .phy_addr = 2, 99 .slave_port = 3, 100 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 101 .phy_if = PHY_INTERFACE_MODE_SGMII, 102 }, 103 { 104 .int_name = "K2E_EMAC3", 105 .rx_flow = 24, 106 .phy_addr = 3, 107 .slave_port = 4, 108 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 109 .phy_if = PHY_INTERFACE_MODE_SGMII, 110 }, 111 { 112 .int_name = "K2E_EMAC4", 113 .rx_flow = 32, 114 .phy_addr = 4, 115 .slave_port = 5, 116 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 117 .phy_if = PHY_INTERFACE_MODE_SGMII, 118 }, 119 { 120 .int_name = "K2E_EMAC5", 121 .rx_flow = 40, 122 .phy_addr = 5, 123 .slave_port = 6, 124 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 125 .phy_if = PHY_INTERFACE_MODE_SGMII, 126 }, 127 { 128 .int_name = "K2E_EMAC6", 129 .rx_flow = 48, 130 .phy_addr = 6, 131 .slave_port = 7, 132 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 133 .phy_if = PHY_INTERFACE_MODE_SGMII, 134 }, 135 { 136 .int_name = "K2E_EMAC7", 137 .rx_flow = 56, 138 .phy_addr = 7, 139 .slave_port = 8, 140 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 141 .phy_if = PHY_INTERFACE_MODE_SGMII, 142 }, 143 }; 144 145 int get_num_eth_ports(void) 146 { 147 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 148 } 149 #endif 150 151 #if defined(CONFIG_BOARD_EARLY_INIT_F) 152 int board_early_init_f(void) 153 { 154 init_plls(); 155 156 return 0; 157 } 158 #endif 159 160 #ifdef CONFIG_SPL_BUILD 161 void spl_init_keystone_plls(void) 162 { 163 init_plls(); 164 } 165 #endif 166