1 /* 2 * Keystone : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include "board.h" 11 #include <common.h> 12 #include <spl.h> 13 #include <exports.h> 14 #include <fdt_support.h> 15 #include <asm/arch/ddr3.h> 16 #include <asm/arch/psc_defs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/ti-common/ti-aemif.h> 19 #include <asm/ti-common/keystone_net.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 static struct aemif_config aemif_configs[] = { 24 { /* CS0 */ 25 .mode = AEMIF_MODE_NAND, 26 .wr_setup = 0xf, 27 .wr_strobe = 0x3f, 28 .wr_hold = 7, 29 .rd_setup = 0xf, 30 .rd_strobe = 0x3f, 31 .rd_hold = 7, 32 .turn_around = 3, 33 .width = AEMIF_WIDTH_8, 34 }, 35 }; 36 37 int dram_init(void) 38 { 39 u32 ddr3_size; 40 41 ddr3_size = ddr3_init(); 42 43 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 44 CONFIG_MAX_RAM_BANK_SIZE); 45 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); 46 if (ddr3_size) 47 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); 48 return 0; 49 } 50 51 int board_init(void) 52 { 53 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 54 55 return 0; 56 } 57 58 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 59 int get_eth_env_param(char *env_name) 60 { 61 char *env; 62 int res = -1; 63 64 env = getenv(env_name); 65 if (env) 66 res = simple_strtol(env, NULL, 0); 67 68 return res; 69 } 70 71 int board_eth_init(bd_t *bis) 72 { 73 int j; 74 int res; 75 int port_num; 76 char link_type_name[32]; 77 78 /* By default, select PA PLL clock as PA clock source */ 79 if (psc_enable_module(KS2_LPSC_PA)) 80 return -1; 81 if (psc_enable_module(KS2_LPSC_CPGMAC)) 82 return -1; 83 if (psc_enable_module(KS2_LPSC_CRYPTO)) 84 return -1; 85 86 if (cpu_is_k2e() || cpu_is_k2l()) 87 pll_pa_clk_sel(); 88 89 port_num = get_num_eth_ports(); 90 91 for (j = 0; j < port_num; j++) { 92 sprintf(link_type_name, "sgmii%d_link_type", j); 93 res = get_eth_env_param(link_type_name); 94 if (res >= 0) 95 eth_priv_cfg[j].sgmii_link_type = res; 96 97 keystone2_emac_initialize(ð_priv_cfg[j]); 98 } 99 100 return 0; 101 } 102 #endif 103 104 #ifdef CONFIG_SPL_BUILD 105 void spl_board_init(void) 106 { 107 spl_init_keystone_plls(); 108 preloader_console_init(); 109 } 110 111 u32 spl_boot_device(void) 112 { 113 #if defined(CONFIG_SPL_SPI_LOAD) 114 return BOOT_DEVICE_SPI; 115 #else 116 puts("Unknown boot device\n"); 117 hang(); 118 #endif 119 } 120 #endif 121 122 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 123 int ft_board_setup(void *blob, bd_t *bd) 124 { 125 int lpae; 126 char *env; 127 char *endp; 128 int nbanks; 129 u64 size[2]; 130 u64 start[2]; 131 int nodeoffset; 132 u32 ddr3a_size; 133 int unitrd_fixup = 0; 134 135 env = getenv("mem_lpae"); 136 lpae = env && simple_strtol(env, NULL, 0); 137 env = getenv("uinitrd_fixup"); 138 unitrd_fixup = env && simple_strtol(env, NULL, 0); 139 140 ddr3a_size = 0; 141 if (lpae) { 142 env = getenv("ddr3a_size"); 143 if (env) 144 ddr3a_size = simple_strtol(env, NULL, 10); 145 if ((ddr3a_size != 8) && (ddr3a_size != 4)) 146 ddr3a_size = 0; 147 } 148 149 nbanks = 1; 150 start[0] = bd->bi_dram[0].start; 151 size[0] = bd->bi_dram[0].size; 152 153 /* adjust memory start address for LPAE */ 154 if (lpae) { 155 start[0] -= CONFIG_SYS_SDRAM_BASE; 156 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; 157 } 158 159 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { 160 size[1] = ((u64)ddr3a_size - 2) << 30; 161 start[1] = 0x880000000; 162 nbanks++; 163 } 164 165 /* reserve memory at start of bank */ 166 env = getenv("mem_reserve_head"); 167 if (env) { 168 start[0] += ustrtoul(env, &endp, 0); 169 size[0] -= ustrtoul(env, &endp, 0); 170 } 171 172 env = getenv("mem_reserve"); 173 if (env) 174 size[0] -= ustrtoul(env, &endp, 0); 175 176 fdt_fixup_memory_banks(blob, start, size, nbanks); 177 178 /* Fix up the initrd */ 179 if (lpae && unitrd_fixup) { 180 int err; 181 u32 *prop1, *prop2; 182 u64 initrd_start, initrd_end; 183 184 nodeoffset = fdt_path_offset(blob, "/chosen"); 185 if (nodeoffset >= 0) { 186 prop1 = (u32 *)fdt_getprop(blob, nodeoffset, 187 "linux,initrd-start", NULL); 188 prop2 = (u32 *)fdt_getprop(blob, nodeoffset, 189 "linux,initrd-end", NULL); 190 if (prop1 && prop2) { 191 initrd_start = __be32_to_cpu(*prop1); 192 initrd_start -= CONFIG_SYS_SDRAM_BASE; 193 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; 194 initrd_start = __cpu_to_be64(initrd_start); 195 initrd_end = __be32_to_cpu(*prop2); 196 initrd_end -= CONFIG_SYS_SDRAM_BASE; 197 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; 198 initrd_end = __cpu_to_be64(initrd_end); 199 200 err = fdt_delprop(blob, nodeoffset, 201 "linux,initrd-start"); 202 if (err < 0) 203 puts("error deleting initrd-start\n"); 204 205 err = fdt_delprop(blob, nodeoffset, 206 "linux,initrd-end"); 207 if (err < 0) 208 puts("error deleting initrd-end\n"); 209 210 err = fdt_setprop(blob, nodeoffset, 211 "linux,initrd-start", 212 &initrd_start, 213 sizeof(initrd_start)); 214 if (err < 0) 215 puts("error adding initrd-start\n"); 216 217 err = fdt_setprop(blob, nodeoffset, 218 "linux,initrd-end", 219 &initrd_end, 220 sizeof(initrd_end)); 221 if (err < 0) 222 puts("error adding linux,initrd-end\n"); 223 } 224 } 225 } 226 227 return 0; 228 } 229 230 void ft_board_setup_ex(void *blob, bd_t *bd) 231 { 232 int lpae; 233 u64 size; 234 char *env; 235 u64 *reserve_start; 236 237 env = getenv("mem_lpae"); 238 lpae = env && simple_strtol(env, NULL, 0); 239 240 if (lpae) { 241 /* 242 * the initrd and other reserved memory areas are 243 * embedded in in the DTB itslef. fix up these addresses 244 * to 36 bit format 245 */ 246 reserve_start = (u64 *)((char *)blob + 247 fdt_off_mem_rsvmap(blob)); 248 while (1) { 249 *reserve_start = __cpu_to_be64(*reserve_start); 250 size = __cpu_to_be64(*(reserve_start + 1)); 251 if (size) { 252 *reserve_start -= CONFIG_SYS_SDRAM_BASE; 253 *reserve_start += 254 CONFIG_SYS_LPAE_SDRAM_BASE; 255 *reserve_start = 256 __cpu_to_be64(*reserve_start); 257 } else { 258 break; 259 } 260 reserve_start += 2; 261 } 262 } 263 264 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); 265 } 266 #endif 267