1 /* 2 * Keystone : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include "board.h" 11 #include <common.h> 12 #include <spl.h> 13 #include <exports.h> 14 #include <fdt_support.h> 15 #include <asm/arch/ddr3.h> 16 #include <asm/arch/psc_defs.h> 17 #include <asm/ti-common/ti-aemif.h> 18 #include <asm/ti-common/keystone_net.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 static struct aemif_config aemif_configs[] = { 23 { /* CS0 */ 24 .mode = AEMIF_MODE_NAND, 25 .wr_setup = 0xf, 26 .wr_strobe = 0x3f, 27 .wr_hold = 7, 28 .rd_setup = 0xf, 29 .rd_strobe = 0x3f, 30 .rd_hold = 7, 31 .turn_around = 3, 32 .width = AEMIF_WIDTH_8, 33 }, 34 }; 35 36 int dram_init(void) 37 { 38 ddr3_init(); 39 40 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 41 CONFIG_MAX_RAM_BANK_SIZE); 42 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); 43 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE); 44 return 0; 45 } 46 47 int board_init(void) 48 { 49 gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; 50 51 return 0; 52 } 53 54 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 55 int get_eth_env_param(char *env_name) 56 { 57 char *env; 58 int res = -1; 59 60 env = getenv(env_name); 61 if (env) 62 res = simple_strtol(env, NULL, 0); 63 64 return res; 65 } 66 67 int board_eth_init(bd_t *bis) 68 { 69 int j; 70 int res; 71 int port_num; 72 char link_type_name[32]; 73 74 /* By default, select PA PLL clock as PA clock source */ 75 if (psc_enable_module(KS2_LPSC_PA)) 76 return -1; 77 if (psc_enable_module(KS2_LPSC_CPGMAC)) 78 return -1; 79 if (psc_enable_module(KS2_LPSC_CRYPTO)) 80 return -1; 81 pass_pll_pa_clk_enable(); 82 83 port_num = get_num_eth_ports(); 84 85 for (j = 0; j < port_num; j++) { 86 sprintf(link_type_name, "sgmii%d_link_type", j); 87 res = get_eth_env_param(link_type_name); 88 if (res >= 0) 89 eth_priv_cfg[j].sgmii_link_type = res; 90 91 keystone2_emac_initialize(ð_priv_cfg[j]); 92 } 93 94 return 0; 95 } 96 #endif 97 98 #ifdef CONFIG_SPL_BUILD 99 void spl_board_init(void) 100 { 101 spl_init_keystone_plls(); 102 preloader_console_init(); 103 } 104 105 u32 spl_boot_device(void) 106 { 107 #if defined(CONFIG_SPL_SPI_LOAD) 108 return BOOT_DEVICE_SPI; 109 #else 110 puts("Unknown boot device\n"); 111 hang(); 112 #endif 113 } 114 #endif 115 116 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 117 int ft_board_setup(void *blob, bd_t *bd) 118 { 119 int lpae; 120 char *env; 121 char *endp; 122 int nbanks; 123 u64 size[2]; 124 u64 start[2]; 125 int nodeoffset; 126 u32 ddr3a_size; 127 int unitrd_fixup = 0; 128 129 env = getenv("mem_lpae"); 130 lpae = env && simple_strtol(env, NULL, 0); 131 env = getenv("uinitrd_fixup"); 132 unitrd_fixup = env && simple_strtol(env, NULL, 0); 133 134 ddr3a_size = 0; 135 if (lpae) { 136 env = getenv("ddr3a_size"); 137 if (env) 138 ddr3a_size = simple_strtol(env, NULL, 10); 139 if ((ddr3a_size != 8) && (ddr3a_size != 4)) 140 ddr3a_size = 0; 141 } 142 143 nbanks = 1; 144 start[0] = bd->bi_dram[0].start; 145 size[0] = bd->bi_dram[0].size; 146 147 /* adjust memory start address for LPAE */ 148 if (lpae) { 149 start[0] -= CONFIG_SYS_SDRAM_BASE; 150 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; 151 } 152 153 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { 154 size[1] = ((u64)ddr3a_size - 2) << 30; 155 start[1] = 0x880000000; 156 nbanks++; 157 } 158 159 /* reserve memory at start of bank */ 160 env = getenv("mem_reserve_head"); 161 if (env) { 162 start[0] += ustrtoul(env, &endp, 0); 163 size[0] -= ustrtoul(env, &endp, 0); 164 } 165 166 env = getenv("mem_reserve"); 167 if (env) 168 size[0] -= ustrtoul(env, &endp, 0); 169 170 fdt_fixup_memory_banks(blob, start, size, nbanks); 171 172 /* Fix up the initrd */ 173 if (lpae && unitrd_fixup) { 174 int err; 175 u32 *prop1, *prop2; 176 u64 initrd_start, initrd_end; 177 178 nodeoffset = fdt_path_offset(blob, "/chosen"); 179 if (nodeoffset >= 0) { 180 prop1 = (u32 *)fdt_getprop(blob, nodeoffset, 181 "linux,initrd-start", NULL); 182 prop2 = (u32 *)fdt_getprop(blob, nodeoffset, 183 "linux,initrd-end", NULL); 184 if (prop1 && prop2) { 185 initrd_start = __be32_to_cpu(*prop1); 186 initrd_start -= CONFIG_SYS_SDRAM_BASE; 187 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; 188 initrd_start = __cpu_to_be64(initrd_start); 189 initrd_end = __be32_to_cpu(*prop2); 190 initrd_end -= CONFIG_SYS_SDRAM_BASE; 191 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; 192 initrd_end = __cpu_to_be64(initrd_end); 193 194 err = fdt_delprop(blob, nodeoffset, 195 "linux,initrd-start"); 196 if (err < 0) 197 puts("error deleting initrd-start\n"); 198 199 err = fdt_delprop(blob, nodeoffset, 200 "linux,initrd-end"); 201 if (err < 0) 202 puts("error deleting initrd-end\n"); 203 204 err = fdt_setprop(blob, nodeoffset, 205 "linux,initrd-start", 206 &initrd_start, 207 sizeof(initrd_start)); 208 if (err < 0) 209 puts("error adding initrd-start\n"); 210 211 err = fdt_setprop(blob, nodeoffset, 212 "linux,initrd-end", 213 &initrd_end, 214 sizeof(initrd_end)); 215 if (err < 0) 216 puts("error adding linux,initrd-end\n"); 217 } 218 } 219 } 220 221 return 0; 222 } 223 224 void ft_board_setup_ex(void *blob, bd_t *bd) 225 { 226 int lpae; 227 u64 size; 228 char *env; 229 u64 *reserve_start; 230 231 env = getenv("mem_lpae"); 232 lpae = env && simple_strtol(env, NULL, 0); 233 234 if (lpae) { 235 /* 236 * the initrd and other reserved memory areas are 237 * embedded in in the DTB itslef. fix up these addresses 238 * to 36 bit format 239 */ 240 reserve_start = (u64 *)((char *)blob + 241 fdt_off_mem_rsvmap(blob)); 242 while (1) { 243 *reserve_start = __cpu_to_be64(*reserve_start); 244 size = __cpu_to_be64(*(reserve_start + 1)); 245 if (size) { 246 *reserve_start -= CONFIG_SYS_SDRAM_BASE; 247 *reserve_start += 248 CONFIG_SYS_LPAE_SDRAM_BASE; 249 *reserve_start = 250 __cpu_to_be64(*reserve_start); 251 } else { 252 break; 253 } 254 reserve_start += 2; 255 } 256 } 257 258 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); 259 } 260 #endif 261