1 /* 2 * Keystone : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include "board.h" 11 #include <common.h> 12 #include <spl.h> 13 #include <exports.h> 14 #include <fdt_support.h> 15 #include <asm/arch/ddr3.h> 16 #include <asm/arch/psc_defs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/ti-common/ti-aemif.h> 19 #include <asm/ti-common/keystone_net.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 static struct aemif_config aemif_configs[] = { 24 { /* CS0 */ 25 .mode = AEMIF_MODE_NAND, 26 .wr_setup = 0xf, 27 .wr_strobe = 0x3f, 28 .wr_hold = 7, 29 .rd_setup = 0xf, 30 .rd_strobe = 0x3f, 31 .rd_hold = 7, 32 .turn_around = 3, 33 .width = AEMIF_WIDTH_8, 34 }, 35 }; 36 37 int dram_init(void) 38 { 39 u32 ddr3_size; 40 41 ddr3_size = ddr3_init(); 42 43 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 44 CONFIG_MAX_RAM_BANK_SIZE); 45 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); 46 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); 47 return 0; 48 } 49 50 int board_init(void) 51 { 52 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 53 54 return 0; 55 } 56 57 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 58 int get_eth_env_param(char *env_name) 59 { 60 char *env; 61 int res = -1; 62 63 env = getenv(env_name); 64 if (env) 65 res = simple_strtol(env, NULL, 0); 66 67 return res; 68 } 69 70 int board_eth_init(bd_t *bis) 71 { 72 int j; 73 int res; 74 int port_num; 75 char link_type_name[32]; 76 77 /* By default, select PA PLL clock as PA clock source */ 78 if (psc_enable_module(KS2_LPSC_PA)) 79 return -1; 80 if (psc_enable_module(KS2_LPSC_CPGMAC)) 81 return -1; 82 if (psc_enable_module(KS2_LPSC_CRYPTO)) 83 return -1; 84 85 if (cpu_is_k2e() || cpu_is_k2l()) 86 pll_pa_clk_sel(); 87 88 port_num = get_num_eth_ports(); 89 90 for (j = 0; j < port_num; j++) { 91 sprintf(link_type_name, "sgmii%d_link_type", j); 92 res = get_eth_env_param(link_type_name); 93 if (res >= 0) 94 eth_priv_cfg[j].sgmii_link_type = res; 95 96 keystone2_emac_initialize(ð_priv_cfg[j]); 97 } 98 99 return 0; 100 } 101 #endif 102 103 #ifdef CONFIG_SPL_BUILD 104 void spl_board_init(void) 105 { 106 spl_init_keystone_plls(); 107 preloader_console_init(); 108 } 109 110 u32 spl_boot_device(void) 111 { 112 #if defined(CONFIG_SPL_SPI_LOAD) 113 return BOOT_DEVICE_SPI; 114 #else 115 puts("Unknown boot device\n"); 116 hang(); 117 #endif 118 } 119 #endif 120 121 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 122 int ft_board_setup(void *blob, bd_t *bd) 123 { 124 int lpae; 125 char *env; 126 char *endp; 127 int nbanks; 128 u64 size[2]; 129 u64 start[2]; 130 int nodeoffset; 131 u32 ddr3a_size; 132 int unitrd_fixup = 0; 133 134 env = getenv("mem_lpae"); 135 lpae = env && simple_strtol(env, NULL, 0); 136 env = getenv("uinitrd_fixup"); 137 unitrd_fixup = env && simple_strtol(env, NULL, 0); 138 139 ddr3a_size = 0; 140 if (lpae) { 141 env = getenv("ddr3a_size"); 142 if (env) 143 ddr3a_size = simple_strtol(env, NULL, 10); 144 if ((ddr3a_size != 8) && (ddr3a_size != 4)) 145 ddr3a_size = 0; 146 } 147 148 nbanks = 1; 149 start[0] = bd->bi_dram[0].start; 150 size[0] = bd->bi_dram[0].size; 151 152 /* adjust memory start address for LPAE */ 153 if (lpae) { 154 start[0] -= CONFIG_SYS_SDRAM_BASE; 155 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; 156 } 157 158 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { 159 size[1] = ((u64)ddr3a_size - 2) << 30; 160 start[1] = 0x880000000; 161 nbanks++; 162 } 163 164 /* reserve memory at start of bank */ 165 env = getenv("mem_reserve_head"); 166 if (env) { 167 start[0] += ustrtoul(env, &endp, 0); 168 size[0] -= ustrtoul(env, &endp, 0); 169 } 170 171 env = getenv("mem_reserve"); 172 if (env) 173 size[0] -= ustrtoul(env, &endp, 0); 174 175 fdt_fixup_memory_banks(blob, start, size, nbanks); 176 177 /* Fix up the initrd */ 178 if (lpae && unitrd_fixup) { 179 int err; 180 u32 *prop1, *prop2; 181 u64 initrd_start, initrd_end; 182 183 nodeoffset = fdt_path_offset(blob, "/chosen"); 184 if (nodeoffset >= 0) { 185 prop1 = (u32 *)fdt_getprop(blob, nodeoffset, 186 "linux,initrd-start", NULL); 187 prop2 = (u32 *)fdt_getprop(blob, nodeoffset, 188 "linux,initrd-end", NULL); 189 if (prop1 && prop2) { 190 initrd_start = __be32_to_cpu(*prop1); 191 initrd_start -= CONFIG_SYS_SDRAM_BASE; 192 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; 193 initrd_start = __cpu_to_be64(initrd_start); 194 initrd_end = __be32_to_cpu(*prop2); 195 initrd_end -= CONFIG_SYS_SDRAM_BASE; 196 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; 197 initrd_end = __cpu_to_be64(initrd_end); 198 199 err = fdt_delprop(blob, nodeoffset, 200 "linux,initrd-start"); 201 if (err < 0) 202 puts("error deleting initrd-start\n"); 203 204 err = fdt_delprop(blob, nodeoffset, 205 "linux,initrd-end"); 206 if (err < 0) 207 puts("error deleting initrd-end\n"); 208 209 err = fdt_setprop(blob, nodeoffset, 210 "linux,initrd-start", 211 &initrd_start, 212 sizeof(initrd_start)); 213 if (err < 0) 214 puts("error adding initrd-start\n"); 215 216 err = fdt_setprop(blob, nodeoffset, 217 "linux,initrd-end", 218 &initrd_end, 219 sizeof(initrd_end)); 220 if (err < 0) 221 puts("error adding linux,initrd-end\n"); 222 } 223 } 224 } 225 226 return 0; 227 } 228 229 void ft_board_setup_ex(void *blob, bd_t *bd) 230 { 231 int lpae; 232 u64 size; 233 char *env; 234 u64 *reserve_start; 235 236 env = getenv("mem_lpae"); 237 lpae = env && simple_strtol(env, NULL, 0); 238 239 if (lpae) { 240 /* 241 * the initrd and other reserved memory areas are 242 * embedded in in the DTB itslef. fix up these addresses 243 * to 36 bit format 244 */ 245 reserve_start = (u64 *)((char *)blob + 246 fdt_off_mem_rsvmap(blob)); 247 while (1) { 248 *reserve_start = __cpu_to_be64(*reserve_start); 249 size = __cpu_to_be64(*(reserve_start + 1)); 250 if (size) { 251 *reserve_start -= CONFIG_SYS_SDRAM_BASE; 252 *reserve_start += 253 CONFIG_SYS_LPAE_SDRAM_BASE; 254 *reserve_start = 255 __cpu_to_be64(*reserve_start); 256 } else { 257 break; 258 } 259 reserve_start += 2; 260 } 261 } 262 263 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); 264 } 265 #endif 266