1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Keystone : Board initialization 4 * 5 * (C) Copyright 2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #include <common.h> 10 #include "board.h" 11 #include <spl.h> 12 #include <exports.h> 13 #include <fdt_support.h> 14 #include <asm/arch/ddr3.h> 15 #include <asm/arch/psc_defs.h> 16 #include <asm/arch/clock.h> 17 #include <asm/ti-common/ti-aemif.h> 18 #include <asm/ti-common/keystone_net.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #if defined(CONFIG_TI_AEMIF) 23 static struct aemif_config aemif_configs[] = { 24 { /* CS0 */ 25 .mode = AEMIF_MODE_NAND, 26 .wr_setup = 0xf, 27 .wr_strobe = 0x3f, 28 .wr_hold = 7, 29 .rd_setup = 0xf, 30 .rd_strobe = 0x3f, 31 .rd_hold = 7, 32 .turn_around = 3, 33 .width = AEMIF_WIDTH_8, 34 }, 35 }; 36 #endif 37 38 int dram_init(void) 39 { 40 u32 ddr3_size; 41 42 ddr3_size = ddr3_init(); 43 44 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 45 CONFIG_MAX_RAM_BANK_SIZE); 46 #if defined(CONFIG_TI_AEMIF) 47 if (!board_is_k2g_ice()) 48 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); 49 #endif 50 51 if (!board_is_k2g_ice()) { 52 if (ddr3_size) 53 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); 54 else 55 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, 56 gd->ram_size >> 30); 57 } 58 59 return 0; 60 } 61 62 int board_init(void) 63 { 64 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 65 66 return 0; 67 } 68 69 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 70 #ifndef CONFIG_DM_ETH 71 int get_eth_env_param(char *env_name) 72 { 73 char *env; 74 int res = -1; 75 76 env = env_get(env_name); 77 if (env) 78 res = simple_strtol(env, NULL, 0); 79 80 return res; 81 } 82 83 int board_eth_init(bd_t *bis) 84 { 85 int j; 86 int res; 87 int port_num; 88 char link_type_name[32]; 89 90 if (cpu_is_k2g()) 91 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); 92 93 /* By default, select PA PLL clock as PA clock source */ 94 #ifndef CONFIG_SOC_K2G 95 if (psc_enable_module(KS2_LPSC_PA)) 96 return -1; 97 #endif 98 if (psc_enable_module(KS2_LPSC_CPGMAC)) 99 return -1; 100 if (psc_enable_module(KS2_LPSC_CRYPTO)) 101 return -1; 102 103 if (cpu_is_k2e() || cpu_is_k2l()) 104 pll_pa_clk_sel(); 105 106 port_num = get_num_eth_ports(); 107 108 for (j = 0; j < port_num; j++) { 109 sprintf(link_type_name, "sgmii%d_link_type", j); 110 res = get_eth_env_param(link_type_name); 111 if (res >= 0) 112 eth_priv_cfg[j].sgmii_link_type = res; 113 114 keystone2_emac_initialize(ð_priv_cfg[j]); 115 } 116 117 return 0; 118 } 119 #endif 120 #endif 121 122 #ifdef CONFIG_SPL_BUILD 123 void spl_board_init(void) 124 { 125 spl_init_keystone_plls(); 126 preloader_console_init(); 127 } 128 129 u32 spl_boot_device(void) 130 { 131 #if defined(CONFIG_SPL_SPI_LOAD) 132 return BOOT_DEVICE_SPI; 133 #else 134 puts("Unknown boot device\n"); 135 hang(); 136 #endif 137 } 138 #endif 139 140 #ifdef CONFIG_OF_BOARD_SETUP 141 int ft_board_setup(void *blob, bd_t *bd) 142 { 143 int lpae; 144 char *env; 145 char *endp; 146 int nbanks; 147 u64 size[2]; 148 u64 start[2]; 149 u32 ddr3a_size; 150 151 env = env_get("mem_lpae"); 152 lpae = env && simple_strtol(env, NULL, 0); 153 154 ddr3a_size = 0; 155 if (lpae) { 156 ddr3a_size = ddr3_get_size(); 157 if ((ddr3a_size != 8) && (ddr3a_size != 4)) 158 ddr3a_size = 0; 159 } 160 161 nbanks = 1; 162 start[0] = bd->bi_dram[0].start; 163 size[0] = bd->bi_dram[0].size; 164 165 /* adjust memory start address for LPAE */ 166 if (lpae) { 167 start[0] -= CONFIG_SYS_SDRAM_BASE; 168 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; 169 } 170 171 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { 172 size[1] = ((u64)ddr3a_size - 2) << 30; 173 start[1] = 0x880000000; 174 nbanks++; 175 } 176 177 /* reserve memory at start of bank */ 178 env = env_get("mem_reserve_head"); 179 if (env) { 180 start[0] += ustrtoul(env, &endp, 0); 181 size[0] -= ustrtoul(env, &endp, 0); 182 } 183 184 env = env_get("mem_reserve"); 185 if (env) 186 size[0] -= ustrtoul(env, &endp, 0); 187 188 fdt_fixup_memory_banks(blob, start, size, nbanks); 189 190 return 0; 191 } 192 193 void ft_board_setup_ex(void *blob, bd_t *bd) 194 { 195 int lpae; 196 u64 size; 197 char *env; 198 u64 *reserve_start; 199 int unitrd_fixup = 0; 200 201 env = env_get("mem_lpae"); 202 lpae = env && simple_strtol(env, NULL, 0); 203 env = env_get("uinitrd_fixup"); 204 unitrd_fixup = env && simple_strtol(env, NULL, 0); 205 206 /* Fix up the initrd */ 207 if (lpae && unitrd_fixup) { 208 int nodeoffset; 209 int err; 210 u64 *prop1, *prop2; 211 u64 initrd_start, initrd_end; 212 213 nodeoffset = fdt_path_offset(blob, "/chosen"); 214 if (nodeoffset >= 0) { 215 prop1 = (u64 *)fdt_getprop(blob, nodeoffset, 216 "linux,initrd-start", NULL); 217 prop2 = (u64 *)fdt_getprop(blob, nodeoffset, 218 "linux,initrd-end", NULL); 219 if (prop1 && prop2) { 220 initrd_start = __be64_to_cpu(*prop1); 221 initrd_start -= CONFIG_SYS_SDRAM_BASE; 222 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; 223 initrd_start = __cpu_to_be64(initrd_start); 224 initrd_end = __be64_to_cpu(*prop2); 225 initrd_end -= CONFIG_SYS_SDRAM_BASE; 226 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; 227 initrd_end = __cpu_to_be64(initrd_end); 228 229 err = fdt_delprop(blob, nodeoffset, 230 "linux,initrd-start"); 231 if (err < 0) 232 puts("error deleting initrd-start\n"); 233 234 err = fdt_delprop(blob, nodeoffset, 235 "linux,initrd-end"); 236 if (err < 0) 237 puts("error deleting initrd-end\n"); 238 239 err = fdt_setprop(blob, nodeoffset, 240 "linux,initrd-start", 241 &initrd_start, 242 sizeof(initrd_start)); 243 if (err < 0) 244 puts("error adding initrd-start\n"); 245 246 err = fdt_setprop(blob, nodeoffset, 247 "linux,initrd-end", 248 &initrd_end, 249 sizeof(initrd_end)); 250 if (err < 0) 251 puts("error adding linux,initrd-end\n"); 252 } 253 } 254 } 255 256 if (lpae) { 257 /* 258 * the initrd and other reserved memory areas are 259 * embedded in in the DTB itslef. fix up these addresses 260 * to 36 bit format 261 */ 262 reserve_start = (u64 *)((char *)blob + 263 fdt_off_mem_rsvmap(blob)); 264 while (1) { 265 *reserve_start = __cpu_to_be64(*reserve_start); 266 size = __cpu_to_be64(*(reserve_start + 1)); 267 if (size) { 268 *reserve_start -= CONFIG_SYS_SDRAM_BASE; 269 *reserve_start += 270 CONFIG_SYS_LPAE_SDRAM_BASE; 271 *reserve_start = 272 __cpu_to_be64(*reserve_start); 273 } else { 274 break; 275 } 276 reserve_start += 2; 277 } 278 } 279 280 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); 281 } 282 #endif /* CONFIG_OF_BOARD_SETUP */ 283 284 #if defined(CONFIG_DTB_RESELECT) 285 int __weak embedded_dtb_select(void) 286 { 287 return 0; 288 } 289 #endif 290