1 /* 2 * Keystone : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include "board.h" 12 #include <spl.h> 13 #include <exports.h> 14 #include <fdt_support.h> 15 #include <asm/arch/ddr3.h> 16 #include <asm/arch/psc_defs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/ti-common/ti-aemif.h> 19 #include <asm/ti-common/keystone_net.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #if defined(CONFIG_TI_AEMIF) 24 static struct aemif_config aemif_configs[] = { 25 { /* CS0 */ 26 .mode = AEMIF_MODE_NAND, 27 .wr_setup = 0xf, 28 .wr_strobe = 0x3f, 29 .wr_hold = 7, 30 .rd_setup = 0xf, 31 .rd_strobe = 0x3f, 32 .rd_hold = 7, 33 .turn_around = 3, 34 .width = AEMIF_WIDTH_8, 35 }, 36 }; 37 #endif 38 39 int dram_init(void) 40 { 41 u32 ddr3_size; 42 43 ddr3_size = ddr3_init(); 44 45 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 46 CONFIG_MAX_RAM_BANK_SIZE); 47 #if defined(CONFIG_TI_AEMIF) 48 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); 49 #endif 50 51 if (ddr3_size) 52 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); 53 return 0; 54 } 55 56 int board_init(void) 57 { 58 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 59 60 return 0; 61 } 62 63 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 64 #ifndef CONFIG_DM_ETH 65 int get_eth_env_param(char *env_name) 66 { 67 char *env; 68 int res = -1; 69 70 env = getenv(env_name); 71 if (env) 72 res = simple_strtol(env, NULL, 0); 73 74 return res; 75 } 76 77 int board_eth_init(bd_t *bis) 78 { 79 int j; 80 int res; 81 int port_num; 82 char link_type_name[32]; 83 84 if (cpu_is_k2g()) 85 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); 86 87 /* By default, select PA PLL clock as PA clock source */ 88 #ifndef CONFIG_SOC_K2G 89 if (psc_enable_module(KS2_LPSC_PA)) 90 return -1; 91 #endif 92 if (psc_enable_module(KS2_LPSC_CPGMAC)) 93 return -1; 94 if (psc_enable_module(KS2_LPSC_CRYPTO)) 95 return -1; 96 97 if (cpu_is_k2e() || cpu_is_k2l()) 98 pll_pa_clk_sel(); 99 100 port_num = get_num_eth_ports(); 101 102 for (j = 0; j < port_num; j++) { 103 sprintf(link_type_name, "sgmii%d_link_type", j); 104 res = get_eth_env_param(link_type_name); 105 if (res >= 0) 106 eth_priv_cfg[j].sgmii_link_type = res; 107 108 keystone2_emac_initialize(ð_priv_cfg[j]); 109 } 110 111 return 0; 112 } 113 #endif 114 #endif 115 116 #ifdef CONFIG_SPL_BUILD 117 void spl_board_init(void) 118 { 119 spl_init_keystone_plls(); 120 preloader_console_init(); 121 } 122 123 u32 spl_boot_device(void) 124 { 125 #if defined(CONFIG_SPL_SPI_LOAD) 126 return BOOT_DEVICE_SPI; 127 #else 128 puts("Unknown boot device\n"); 129 hang(); 130 #endif 131 } 132 #endif 133 134 #ifdef CONFIG_OF_BOARD_SETUP 135 int ft_board_setup(void *blob, bd_t *bd) 136 { 137 int lpae; 138 char *env; 139 char *endp; 140 int nbanks; 141 u64 size[2]; 142 u64 start[2]; 143 int nodeoffset; 144 u32 ddr3a_size; 145 int unitrd_fixup = 0; 146 147 env = getenv("mem_lpae"); 148 lpae = env && simple_strtol(env, NULL, 0); 149 env = getenv("uinitrd_fixup"); 150 unitrd_fixup = env && simple_strtol(env, NULL, 0); 151 152 ddr3a_size = 0; 153 if (lpae) { 154 ddr3a_size = ddr3_get_size(); 155 if ((ddr3a_size != 8) && (ddr3a_size != 4)) 156 ddr3a_size = 0; 157 } 158 159 nbanks = 1; 160 start[0] = bd->bi_dram[0].start; 161 size[0] = bd->bi_dram[0].size; 162 163 /* adjust memory start address for LPAE */ 164 if (lpae) { 165 start[0] -= CONFIG_SYS_SDRAM_BASE; 166 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; 167 } 168 169 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { 170 size[1] = ((u64)ddr3a_size - 2) << 30; 171 start[1] = 0x880000000; 172 nbanks++; 173 } 174 175 /* reserve memory at start of bank */ 176 env = getenv("mem_reserve_head"); 177 if (env) { 178 start[0] += ustrtoul(env, &endp, 0); 179 size[0] -= ustrtoul(env, &endp, 0); 180 } 181 182 env = getenv("mem_reserve"); 183 if (env) 184 size[0] -= ustrtoul(env, &endp, 0); 185 186 fdt_fixup_memory_banks(blob, start, size, nbanks); 187 188 /* Fix up the initrd */ 189 if (lpae && unitrd_fixup) { 190 int err; 191 u32 *prop1, *prop2; 192 u64 initrd_start, initrd_end; 193 194 nodeoffset = fdt_path_offset(blob, "/chosen"); 195 if (nodeoffset >= 0) { 196 prop1 = (u32 *)fdt_getprop(blob, nodeoffset, 197 "linux,initrd-start", NULL); 198 prop2 = (u32 *)fdt_getprop(blob, nodeoffset, 199 "linux,initrd-end", NULL); 200 if (prop1 && prop2) { 201 initrd_start = __be32_to_cpu(*prop1); 202 initrd_start -= CONFIG_SYS_SDRAM_BASE; 203 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; 204 initrd_start = __cpu_to_be64(initrd_start); 205 initrd_end = __be32_to_cpu(*prop2); 206 initrd_end -= CONFIG_SYS_SDRAM_BASE; 207 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; 208 initrd_end = __cpu_to_be64(initrd_end); 209 210 err = fdt_delprop(blob, nodeoffset, 211 "linux,initrd-start"); 212 if (err < 0) 213 puts("error deleting initrd-start\n"); 214 215 err = fdt_delprop(blob, nodeoffset, 216 "linux,initrd-end"); 217 if (err < 0) 218 puts("error deleting initrd-end\n"); 219 220 err = fdt_setprop(blob, nodeoffset, 221 "linux,initrd-start", 222 &initrd_start, 223 sizeof(initrd_start)); 224 if (err < 0) 225 puts("error adding initrd-start\n"); 226 227 err = fdt_setprop(blob, nodeoffset, 228 "linux,initrd-end", 229 &initrd_end, 230 sizeof(initrd_end)); 231 if (err < 0) 232 puts("error adding linux,initrd-end\n"); 233 } 234 } 235 } 236 237 return 0; 238 } 239 240 void ft_board_setup_ex(void *blob, bd_t *bd) 241 { 242 int lpae; 243 u64 size; 244 char *env; 245 u64 *reserve_start; 246 247 env = getenv("mem_lpae"); 248 lpae = env && simple_strtol(env, NULL, 0); 249 250 if (lpae) { 251 /* 252 * the initrd and other reserved memory areas are 253 * embedded in in the DTB itslef. fix up these addresses 254 * to 36 bit format 255 */ 256 reserve_start = (u64 *)((char *)blob + 257 fdt_off_mem_rsvmap(blob)); 258 while (1) { 259 *reserve_start = __cpu_to_be64(*reserve_start); 260 size = __cpu_to_be64(*(reserve_start + 1)); 261 if (size) { 262 *reserve_start -= CONFIG_SYS_SDRAM_BASE; 263 *reserve_start += 264 CONFIG_SYS_LPAE_SDRAM_BASE; 265 *reserve_start = 266 __cpu_to_be64(*reserve_start); 267 } else { 268 break; 269 } 270 reserve_start += 2; 271 } 272 } 273 274 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); 275 } 276 #endif /* CONFIG_OF_BOARD_SETUP */ 277