1 /* 2 * Keystone : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include "board.h" 11 #include <common.h> 12 #include <spl.h> 13 #include <exports.h> 14 #include <fdt_support.h> 15 #include <asm/arch/ddr3.h> 16 #include <asm/arch/psc_defs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/ti-common/ti-aemif.h> 19 #include <asm/ti-common/keystone_net.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 static struct aemif_config aemif_configs[] = { 24 { /* CS0 */ 25 .mode = AEMIF_MODE_NAND, 26 .wr_setup = 0xf, 27 .wr_strobe = 0x3f, 28 .wr_hold = 7, 29 .rd_setup = 0xf, 30 .rd_strobe = 0x3f, 31 .rd_hold = 7, 32 .turn_around = 3, 33 .width = AEMIF_WIDTH_8, 34 }, 35 }; 36 37 int dram_init(void) 38 { 39 u32 ddr3_size; 40 41 ddr3_size = ddr3_init(); 42 43 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 44 CONFIG_MAX_RAM_BANK_SIZE); 45 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); 46 if (ddr3_size) 47 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); 48 return 0; 49 } 50 51 int board_init(void) 52 { 53 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 54 55 return 0; 56 } 57 58 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 59 int get_eth_env_param(char *env_name) 60 { 61 char *env; 62 int res = -1; 63 64 env = getenv(env_name); 65 if (env) 66 res = simple_strtol(env, NULL, 0); 67 68 return res; 69 } 70 71 int board_eth_init(bd_t *bis) 72 { 73 int j; 74 int res; 75 int port_num; 76 char link_type_name[32]; 77 78 if (cpu_is_k2g()) 79 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); 80 81 /* By default, select PA PLL clock as PA clock source */ 82 #ifndef CONFIG_SOC_K2G 83 if (psc_enable_module(KS2_LPSC_PA)) 84 return -1; 85 #endif 86 if (psc_enable_module(KS2_LPSC_CPGMAC)) 87 return -1; 88 if (psc_enable_module(KS2_LPSC_CRYPTO)) 89 return -1; 90 91 if (cpu_is_k2e() || cpu_is_k2l()) 92 pll_pa_clk_sel(); 93 94 port_num = get_num_eth_ports(); 95 96 for (j = 0; j < port_num; j++) { 97 sprintf(link_type_name, "sgmii%d_link_type", j); 98 res = get_eth_env_param(link_type_name); 99 if (res >= 0) 100 eth_priv_cfg[j].sgmii_link_type = res; 101 102 keystone2_emac_initialize(ð_priv_cfg[j]); 103 } 104 105 return 0; 106 } 107 #endif 108 109 #ifdef CONFIG_SPL_BUILD 110 void spl_board_init(void) 111 { 112 spl_init_keystone_plls(); 113 preloader_console_init(); 114 } 115 116 u32 spl_boot_device(void) 117 { 118 #if defined(CONFIG_SPL_SPI_LOAD) 119 return BOOT_DEVICE_SPI; 120 #else 121 puts("Unknown boot device\n"); 122 hang(); 123 #endif 124 } 125 #endif 126 127 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 128 int ft_board_setup(void *blob, bd_t *bd) 129 { 130 int lpae; 131 char *env; 132 char *endp; 133 int nbanks; 134 u64 size[2]; 135 u64 start[2]; 136 int nodeoffset; 137 u32 ddr3a_size; 138 int unitrd_fixup = 0; 139 140 env = getenv("mem_lpae"); 141 lpae = env && simple_strtol(env, NULL, 0); 142 env = getenv("uinitrd_fixup"); 143 unitrd_fixup = env && simple_strtol(env, NULL, 0); 144 145 ddr3a_size = 0; 146 if (lpae) { 147 env = getenv("ddr3a_size"); 148 if (env) 149 ddr3a_size = simple_strtol(env, NULL, 10); 150 if ((ddr3a_size != 8) && (ddr3a_size != 4)) 151 ddr3a_size = 0; 152 } 153 154 nbanks = 1; 155 start[0] = bd->bi_dram[0].start; 156 size[0] = bd->bi_dram[0].size; 157 158 /* adjust memory start address for LPAE */ 159 if (lpae) { 160 start[0] -= CONFIG_SYS_SDRAM_BASE; 161 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; 162 } 163 164 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { 165 size[1] = ((u64)ddr3a_size - 2) << 30; 166 start[1] = 0x880000000; 167 nbanks++; 168 } 169 170 /* reserve memory at start of bank */ 171 env = getenv("mem_reserve_head"); 172 if (env) { 173 start[0] += ustrtoul(env, &endp, 0); 174 size[0] -= ustrtoul(env, &endp, 0); 175 } 176 177 env = getenv("mem_reserve"); 178 if (env) 179 size[0] -= ustrtoul(env, &endp, 0); 180 181 fdt_fixup_memory_banks(blob, start, size, nbanks); 182 183 /* Fix up the initrd */ 184 if (lpae && unitrd_fixup) { 185 int err; 186 u32 *prop1, *prop2; 187 u64 initrd_start, initrd_end; 188 189 nodeoffset = fdt_path_offset(blob, "/chosen"); 190 if (nodeoffset >= 0) { 191 prop1 = (u32 *)fdt_getprop(blob, nodeoffset, 192 "linux,initrd-start", NULL); 193 prop2 = (u32 *)fdt_getprop(blob, nodeoffset, 194 "linux,initrd-end", NULL); 195 if (prop1 && prop2) { 196 initrd_start = __be32_to_cpu(*prop1); 197 initrd_start -= CONFIG_SYS_SDRAM_BASE; 198 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; 199 initrd_start = __cpu_to_be64(initrd_start); 200 initrd_end = __be32_to_cpu(*prop2); 201 initrd_end -= CONFIG_SYS_SDRAM_BASE; 202 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; 203 initrd_end = __cpu_to_be64(initrd_end); 204 205 err = fdt_delprop(blob, nodeoffset, 206 "linux,initrd-start"); 207 if (err < 0) 208 puts("error deleting initrd-start\n"); 209 210 err = fdt_delprop(blob, nodeoffset, 211 "linux,initrd-end"); 212 if (err < 0) 213 puts("error deleting initrd-end\n"); 214 215 err = fdt_setprop(blob, nodeoffset, 216 "linux,initrd-start", 217 &initrd_start, 218 sizeof(initrd_start)); 219 if (err < 0) 220 puts("error adding initrd-start\n"); 221 222 err = fdt_setprop(blob, nodeoffset, 223 "linux,initrd-end", 224 &initrd_end, 225 sizeof(initrd_end)); 226 if (err < 0) 227 puts("error adding linux,initrd-end\n"); 228 } 229 } 230 } 231 232 return 0; 233 } 234 235 void ft_board_setup_ex(void *blob, bd_t *bd) 236 { 237 int lpae; 238 u64 size; 239 char *env; 240 u64 *reserve_start; 241 242 env = getenv("mem_lpae"); 243 lpae = env && simple_strtol(env, NULL, 0); 244 245 if (lpae) { 246 /* 247 * the initrd and other reserved memory areas are 248 * embedded in in the DTB itslef. fix up these addresses 249 * to 36 bit format 250 */ 251 reserve_start = (u64 *)((char *)blob + 252 fdt_off_mem_rsvmap(blob)); 253 while (1) { 254 *reserve_start = __cpu_to_be64(*reserve_start); 255 size = __cpu_to_be64(*(reserve_start + 1)); 256 if (size) { 257 *reserve_start -= CONFIG_SYS_SDRAM_BASE; 258 *reserve_start += 259 CONFIG_SYS_LPAE_SDRAM_BASE; 260 *reserve_start = 261 __cpu_to_be64(*reserve_start); 262 } else { 263 break; 264 } 265 reserve_start += 2; 266 } 267 } 268 269 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE); 270 } 271 #endif 272