1 /* 2 * (C) Copyright 2004-2011 3 * Texas Instruments, <www.ti.com> 4 * 5 * Author : 6 * Manikandan Pillai <mani.pillai@ti.com> 7 * 8 * Derived from Beagle Board and 3430 SDP code by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 #include <common.h> 31 #include <netdev.h> 32 #include <asm/io.h> 33 #include <asm/arch/mem.h> 34 #include <asm/arch/mux.h> 35 #include <asm/arch/sys_proto.h> 36 #include <asm/arch/mmc_host_def.h> 37 #include <asm/gpio.h> 38 #include <i2c.h> 39 #include <asm/mach-types.h> 40 #include <linux/mtd/nand.h> 41 #include "evm.h" 42 43 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 44 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 static u32 omap3_evm_version; 49 50 u32 get_omap3_evm_rev(void) 51 { 52 return omap3_evm_version; 53 } 54 55 static void omap3_evm_get_revision(void) 56 { 57 #if defined(CONFIG_CMD_NET) 58 /* 59 * Board revision can be ascertained only by identifying 60 * the Ethernet chipset. 61 */ 62 unsigned int smsc_id; 63 64 /* Ethernet PHY ID is stored at ID_REV register */ 65 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; 66 printf("Read back SMSC id 0x%x\n", smsc_id); 67 68 switch (smsc_id) { 69 /* SMSC9115 chipset */ 70 case 0x01150000: 71 omap3_evm_version = OMAP3EVM_BOARD_GEN_1; 72 break; 73 /* SMSC 9220 chipset */ 74 case 0x92200000: 75 default: 76 omap3_evm_version = OMAP3EVM_BOARD_GEN_2; 77 } 78 #else 79 #if defined(CONFIG_STATIC_BOARD_REV) 80 /* 81 * Look for static defintion of the board revision 82 */ 83 omap3_evm_version = CONFIG_STATIC_BOARD_REV; 84 #else 85 /* 86 * Fallback to the default above. 87 */ 88 omap3_evm_version = OMAP3EVM_BOARD_GEN_2; 89 #endif 90 #endif /* CONFIG_CMD_NET */ 91 } 92 93 #ifdef CONFIG_USB_OMAP3 94 /* 95 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. 96 */ 97 u8 omap3_evm_need_extvbus(void) 98 { 99 u8 retval = 0; 100 101 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 102 retval = 1; 103 104 return retval; 105 } 106 #endif 107 108 /* 109 * Routine: board_init 110 * Description: Early hardware init. 111 */ 112 int board_init(void) 113 { 114 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 115 /* board id for Linux */ 116 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; 117 /* boot param addr */ 118 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 119 120 return 0; 121 } 122 123 #ifdef CONFIG_SPL_BUILD 124 /* 125 * Routine: get_board_mem_timings 126 * Description: If we use SPL then there is no x-loader nor config header 127 * so we have to setup the DDR timings ourself on the first bank. This 128 * provides the timing values back to the function that configures 129 * the memory. 130 */ 131 void get_board_mem_timings(struct board_sdrc_timings *timings) 132 { 133 int pop_mfr, pop_id; 134 135 /* 136 * We need to identify what PoP memory is on the board so that 137 * we know what timings to use. To map the ID values please see 138 * nand_ids.c 139 */ 140 identify_nand_chip(&pop_mfr, &pop_id); 141 142 if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { 143 /* 256MB DDR */ 144 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 145 timings->ctrla = HYNIX_V_ACTIMA_200; 146 timings->ctrlb = HYNIX_V_ACTIMB_200; 147 } else { 148 /* 128MB DDR */ 149 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 150 timings->ctrla = MICRON_V_ACTIMA_165; 151 timings->ctrlb = MICRON_V_ACTIMB_165; 152 } 153 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 154 timings->mr = MICRON_V_MR_165; 155 } 156 #endif 157 158 /* 159 * Routine: misc_init_r 160 * Description: Init ethernet (done here so udelay works) 161 */ 162 int misc_init_r(void) 163 { 164 165 #ifdef CONFIG_DRIVER_OMAP34XX_I2C 166 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 167 #endif 168 169 #if defined(CONFIG_CMD_NET) 170 setup_net_chip(); 171 #endif 172 omap3_evm_get_revision(); 173 174 #if defined(CONFIG_CMD_NET) 175 reset_net_chip(); 176 #endif 177 dieid_num_r(); 178 179 return 0; 180 } 181 182 /* 183 * Routine: set_muxconf_regs 184 * Description: Setting up the configuration Mux registers specific to the 185 * hardware. Many pins need to be moved from protect to primary 186 * mode. 187 */ 188 void set_muxconf_regs(void) 189 { 190 MUX_EVM(); 191 } 192 193 #ifdef CONFIG_CMD_NET 194 /* 195 * Routine: setup_net_chip 196 * Description: Setting up the configuration GPMC registers specific to the 197 * Ethernet hardware. 198 */ 199 static void setup_net_chip(void) 200 { 201 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 202 203 /* Configure GPMC registers */ 204 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); 205 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); 206 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); 207 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); 208 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); 209 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); 210 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); 211 212 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 213 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 214 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 215 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 216 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 217 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 218 &ctrl_base->gpmc_nadv_ale); 219 } 220 221 /** 222 * Reset the ethernet chip. 223 */ 224 static void reset_net_chip(void) 225 { 226 int ret; 227 int rst_gpio; 228 229 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) { 230 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1; 231 } else { 232 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2; 233 } 234 235 ret = gpio_request(rst_gpio, ""); 236 if (ret < 0) { 237 printf("Unable to get GPIO %d\n", rst_gpio); 238 return ; 239 } 240 241 /* Configure as output */ 242 gpio_direction_output(rst_gpio, 0); 243 244 /* Send a pulse on the GPIO pin */ 245 gpio_set_value(rst_gpio, 1); 246 udelay(1); 247 gpio_set_value(rst_gpio, 0); 248 udelay(1); 249 gpio_set_value(rst_gpio, 1); 250 } 251 252 int board_eth_init(bd_t *bis) 253 { 254 int rc = 0; 255 #ifdef CONFIG_SMC911X 256 #define STR_ENV_ETHADDR "ethaddr" 257 258 struct eth_device *dev; 259 uchar eth_addr[6]; 260 261 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 262 263 if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { 264 dev = eth_get_dev_by_index(0); 265 if (dev) { 266 eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); 267 } else { 268 printf("omap3evm: Couldn't get eth device\n"); 269 rc = -1; 270 } 271 } 272 #endif 273 return rc; 274 } 275 #endif /* CONFIG_CMD_NET */ 276 277 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 278 int board_mmc_init(bd_t *bis) 279 { 280 return omap_mmc_init(0, 0, 0, -1); 281 } 282 #endif 283