1 /* 2 * (C) Copyright 2004-2011 3 * Texas Instruments, <www.ti.com> 4 * 5 * Author : 6 * Manikandan Pillai <mani.pillai@ti.com> 7 * 8 * Derived from Beagle Board and 3430 SDP code by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 #include <common.h> 15 #include <dm.h> 16 #include <ns16550.h> 17 #include <netdev.h> 18 #include <asm/io.h> 19 #include <asm/arch/mem.h> 20 #include <asm/arch/mux.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/gpio.h> 24 #include <i2c.h> 25 #include <twl4030.h> 26 #include <asm/mach-types.h> 27 #include <asm/omap_musb.h> 28 #include <linux/mtd/nand.h> 29 #include <linux/usb/ch9.h> 30 #include <linux/usb/gadget.h> 31 #include <linux/usb/musb.h> 32 #include "evm.h" 33 34 #ifdef CONFIG_USB_EHCI_HCD 35 #include <usb.h> 36 #include <asm/ehci-omap.h> 37 #endif 38 39 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 40 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 static const struct ns16550_platdata omap3_evm_serial = { 45 .base = OMAP34XX_UART1, 46 .reg_shift = 2, 47 .clock = V_NS16550_CLK, 48 .fcr = UART_FCR_DEFVAL, 49 }; 50 51 U_BOOT_DEVICE(omap3_evm_uart) = { 52 "ns16550_serial", 53 &omap3_evm_serial 54 }; 55 56 static u32 omap3_evm_version; 57 58 u32 get_omap3_evm_rev(void) 59 { 60 return omap3_evm_version; 61 } 62 63 static void omap3_evm_get_revision(void) 64 { 65 #if defined(CONFIG_CMD_NET) 66 /* 67 * Board revision can be ascertained only by identifying 68 * the Ethernet chipset. 69 */ 70 unsigned int smsc_id; 71 72 /* Ethernet PHY ID is stored at ID_REV register */ 73 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; 74 printf("Read back SMSC id 0x%x\n", smsc_id); 75 76 switch (smsc_id) { 77 /* SMSC9115 chipset */ 78 case 0x01150000: 79 omap3_evm_version = OMAP3EVM_BOARD_GEN_1; 80 break; 81 /* SMSC 9220 chipset */ 82 case 0x92200000: 83 default: 84 omap3_evm_version = OMAP3EVM_BOARD_GEN_2; 85 } 86 #else /* !CONFIG_CMD_NET */ 87 #if defined(CONFIG_STATIC_BOARD_REV) 88 /* Look for static defintion of the board revision */ 89 omap3_evm_version = CONFIG_STATIC_BOARD_REV; 90 #else 91 /* Fallback to the default above */ 92 omap3_evm_version = OMAP3EVM_BOARD_GEN_2; 93 #endif /* CONFIG_STATIC_BOARD_REV */ 94 #endif /* CONFIG_CMD_NET */ 95 } 96 97 #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST) 98 /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */ 99 u8 omap3_evm_need_extvbus(void) 100 { 101 u8 retval = 0; 102 103 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 104 retval = 1; 105 106 return retval; 107 } 108 #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */ 109 110 /* 111 * Routine: board_init 112 * Description: Early hardware init. 113 */ 114 int board_init(void) 115 { 116 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 117 /* board id for Linux */ 118 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; 119 /* boot param addr */ 120 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 121 122 return 0; 123 } 124 125 #if defined(CONFIG_SPL_OS_BOOT) 126 int spl_start_uboot(void) 127 { 128 /* break into full u-boot on 'c' */ 129 if (serial_tstc() && serial_getc() == 'c') 130 return 1; 131 132 return 0; 133 } 134 #endif /* CONFIG_SPL_OS_BOOT */ 135 136 #if defined(CONFIG_SPL_BUILD) 137 /* 138 * Routine: get_board_mem_timings 139 * Description: If we use SPL then there is no x-loader nor config header 140 * so we have to setup the DDR timings ourself on the first bank. This 141 * provides the timing values back to the function that configures 142 * the memory. 143 */ 144 void get_board_mem_timings(struct board_sdrc_timings *timings) 145 { 146 int pop_mfr, pop_id; 147 148 /* 149 * We need to identify what PoP memory is on the board so that 150 * we know what timings to use. To map the ID values please see 151 * nand_ids.c 152 */ 153 identify_nand_chip(&pop_mfr, &pop_id); 154 155 if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { 156 /* 256MB DDR */ 157 timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 158 timings->ctrla = HYNIX_V_ACTIMA_200; 159 timings->ctrlb = HYNIX_V_ACTIMB_200; 160 } else { 161 /* 128MB DDR */ 162 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 163 timings->ctrla = MICRON_V_ACTIMA_165; 164 timings->ctrlb = MICRON_V_ACTIMB_165; 165 } 166 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 167 timings->mr = MICRON_V_MR_165; 168 } 169 #endif /* CONFIG_SPL_BUILD */ 170 171 #if defined(CONFIG_USB_MUSB_OMAP2PLUS) 172 static struct musb_hdrc_config musb_config = { 173 .multipoint = 1, 174 .dyn_fifo = 1, 175 .num_eps = 16, 176 .ram_bits = 12, 177 }; 178 179 static struct omap_musb_board_data musb_board_data = { 180 .interface_type = MUSB_INTERFACE_ULPI, 181 }; 182 183 static struct musb_hdrc_platform_data musb_plat = { 184 #if defined(CONFIG_USB_MUSB_HOST) 185 .mode = MUSB_HOST, 186 #elif defined(CONFIG_USB_MUSB_GADGET) 187 .mode = MUSB_PERIPHERAL, 188 #else 189 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" 190 #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */ 191 .config = &musb_config, 192 .power = 100, 193 .platform_ops = &omap2430_ops, 194 .board_data = &musb_board_data, 195 }; 196 #endif /* CONFIG_USB_MUSB_OMAP2PLUS */ 197 198 /* 199 * Routine: misc_init_r 200 * Description: Init ethernet (done here so udelay works) 201 */ 202 int misc_init_r(void) 203 { 204 twl4030_power_init(); 205 206 #ifdef CONFIG_SYS_I2C_OMAP24XX 207 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 208 #endif 209 210 #if defined(CONFIG_CMD_NET) 211 setup_net_chip(); 212 #endif 213 omap3_evm_get_revision(); 214 215 #if defined(CONFIG_CMD_NET) 216 reset_net_chip(); 217 #endif 218 omap_die_id_display(); 219 220 #if defined(CONFIG_USB_MUSB_OMAP2PLUS) 221 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); 222 #endif 223 224 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) 225 omap_die_id_usbethaddr(); 226 #endif 227 return 0; 228 } 229 230 /* 231 * Routine: set_muxconf_regs 232 * Description: Setting up the configuration Mux registers specific to the 233 * hardware. Many pins need to be moved from protect to primary 234 * mode. 235 */ 236 void set_muxconf_regs(void) 237 { 238 MUX_EVM(); 239 } 240 241 #if defined(CONFIG_CMD_NET) 242 /* 243 * Routine: setup_net_chip 244 * Description: Setting up the configuration GPMC registers specific to the 245 * Ethernet hardware. 246 */ 247 static void setup_net_chip(void) 248 { 249 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 250 251 /* Configure GPMC registers */ 252 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); 253 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); 254 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); 255 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); 256 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); 257 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); 258 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); 259 260 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 261 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 262 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 263 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 264 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 265 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 266 &ctrl_base->gpmc_nadv_ale); 267 } 268 269 /** 270 * Reset the ethernet chip. 271 */ 272 static void reset_net_chip(void) 273 { 274 int ret; 275 int rst_gpio; 276 277 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) { 278 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1; 279 } else { 280 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2; 281 } 282 283 ret = gpio_request(rst_gpio, ""); 284 if (ret < 0) { 285 printf("Unable to get GPIO %d\n", rst_gpio); 286 return ; 287 } 288 289 /* Configure as output */ 290 gpio_direction_output(rst_gpio, 0); 291 292 /* Send a pulse on the GPIO pin */ 293 gpio_set_value(rst_gpio, 1); 294 udelay(1); 295 gpio_set_value(rst_gpio, 0); 296 udelay(1); 297 gpio_set_value(rst_gpio, 1); 298 } 299 300 int board_eth_init(bd_t *bis) 301 { 302 int rc = 0; 303 #if defined(CONFIG_SMC911X) 304 #define STR_ENV_ETHADDR "ethaddr" 305 306 struct eth_device *dev; 307 uchar eth_addr[6]; 308 309 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 310 311 if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) { 312 dev = eth_get_dev_by_index(0); 313 if (dev) { 314 eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); 315 } else { 316 printf("omap3evm: Couldn't get eth device\n"); 317 rc = -1; 318 } 319 } 320 #endif /* CONFIG_SMC911X */ 321 return rc; 322 } 323 #endif /* CONFIG_CMD_NET */ 324 325 #if defined(CONFIG_MMC) 326 int board_mmc_init(bd_t *bis) 327 { 328 return omap_mmc_init(0, 0, 0, -1, -1); 329 } 330 331 void board_mmc_power_init(void) 332 { 333 twl4030_power_mmc_init(0); 334 } 335 #endif /* CONFIG_MMC */ 336 337 #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) 338 /* Call usb_stop() before starting the kernel */ 339 void show_boot_progress(int val) 340 { 341 if (val == BOOTSTAGE_ID_RUN_OS) 342 usb_stop(); 343 } 344 345 static struct omap_usbhs_board_data usbhs_bdata = { 346 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, 347 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 348 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED 349 }; 350 351 int ehci_hcd_init(int index, enum usb_init_type init, 352 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 353 { 354 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 355 } 356 357 int ehci_hcd_stop(int index) 358 { 359 return omap_ehci_hcd_stop(); 360 } 361 #endif /* CONFIG_USB_EHCI_HCD */ 362 363 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET) 364 int board_eth_init(bd_t *bis) 365 { 366 return usb_eth_initialize(bis); 367 } 368 #endif /* CONFIG_USB_ETHER */ 369