xref: /openbmc/u-boot/board/ti/evm/evm.c (revision cbd2fba1) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2004-2011
4  * Texas Instruments, <www.ti.com>
5  *
6  * Author :
7  *	Manikandan Pillai <mani.pillai@ti.com>
8  *
9  * Derived from Beagle Board and 3430 SDP code by
10  *	Richard Woodruff <r-woodruff2@ti.com>
11  *	Syed Mohammed Khasim <khasim@ti.com>
12  */
13 #include <common.h>
14 #include <dm.h>
15 #include <ns16550.h>
16 #include <netdev.h>
17 #include <asm/io.h>
18 #include <asm/arch/mem.h>
19 #include <asm/arch/mux.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/gpio.h>
23 #include <i2c.h>
24 #include <twl4030.h>
25 #include <asm/mach-types.h>
26 #include <asm/omap_musb.h>
27 #include <linux/mtd/rawnand.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/musb.h>
31 #include "evm.h"
32 
33 #ifdef CONFIG_USB_EHCI_HCD
34 #include <usb.h>
35 #include <asm/ehci-omap.h>
36 #endif
37 
38 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
39 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
40 
41 DECLARE_GLOBAL_DATA_PTR;
42 
43 static const struct ns16550_platdata omap3_evm_serial = {
44 	.base = OMAP34XX_UART1,
45 	.reg_shift = 2,
46 	.clock = V_NS16550_CLK,
47 	.fcr = UART_FCR_DEFVAL,
48 };
49 
50 U_BOOT_DEVICE(omap3_evm_uart) = {
51 	"ns16550_serial",
52 	&omap3_evm_serial
53 };
54 
55 static u32 omap3_evm_version;
56 
57 u32 get_omap3_evm_rev(void)
58 {
59 	return omap3_evm_version;
60 }
61 
62 static void omap3_evm_get_revision(void)
63 {
64 #if defined(CONFIG_CMD_NET)
65 	/*
66 	 * Board revision can be ascertained only by identifying
67 	 * the Ethernet chipset.
68 	 */
69 	unsigned int smsc_id;
70 
71 	/* Ethernet PHY ID is stored at ID_REV register */
72 	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
73 	printf("Read back SMSC id 0x%x\n", smsc_id);
74 
75 	switch (smsc_id) {
76 	/* SMSC9115 chipset */
77 	case 0x01150000:
78 		omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
79 		break;
80 	/* SMSC 9220 chipset */
81 	case 0x92200000:
82 	default:
83 		omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
84        }
85 #else /* !CONFIG_CMD_NET */
86 #if defined(CONFIG_STATIC_BOARD_REV)
87 	/* Look for static defintion of the board revision */
88 	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
89 #else
90 	/* Fallback to the default above */
91 	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
92 #endif /* CONFIG_STATIC_BOARD_REV */
93 #endif /* CONFIG_CMD_NET */
94 }
95 
96 #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
97 /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
98 u8 omap3_evm_need_extvbus(void)
99 {
100 	u8 retval = 0;
101 
102 	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
103 		retval = 1;
104 
105 	return retval;
106 }
107 #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
108 
109 /*
110  * Routine: board_init
111  * Description: Early hardware init.
112  */
113 int board_init(void)
114 {
115 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
116 	/* board id for Linux */
117 	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
118 	/* boot param addr */
119 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
120 
121 	return 0;
122 }
123 
124 #if defined(CONFIG_SPL_OS_BOOT)
125 int spl_start_uboot(void)
126 {
127 	/* break into full u-boot on 'c' */
128 	if (serial_tstc() && serial_getc() == 'c')
129 		return 1;
130 
131 	return 0;
132 }
133 #endif /* CONFIG_SPL_OS_BOOT */
134 
135 #if defined(CONFIG_SPL_BUILD)
136 /*
137  * Routine: get_board_mem_timings
138  * Description: If we use SPL then there is no x-loader nor config header
139  * so we have to setup the DDR timings ourself on the first bank.  This
140  * provides the timing values back to the function that configures
141  * the memory.
142  */
143 void get_board_mem_timings(struct board_sdrc_timings *timings)
144 {
145 	int pop_mfr, pop_id;
146 
147 	/*
148 	 * We need to identify what PoP memory is on the board so that
149 	 * we know what timings to use.  To map the ID values please see
150 	 * nand_ids.c
151 	 */
152 	identify_nand_chip(&pop_mfr, &pop_id);
153 
154 	if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
155 		/* 256MB DDR */
156 		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
157 		timings->ctrla = HYNIX_V_ACTIMA_200;
158 		timings->ctrlb = HYNIX_V_ACTIMB_200;
159 	} else {
160 		/* 128MB DDR */
161 		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
162 		timings->ctrla = MICRON_V_ACTIMA_165;
163 		timings->ctrlb = MICRON_V_ACTIMB_165;
164 	}
165 	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
166 	timings->mr = MICRON_V_MR_165;
167 }
168 #endif /* CONFIG_SPL_BUILD */
169 
170 #if defined(CONFIG_USB_MUSB_OMAP2PLUS)
171 static struct musb_hdrc_config musb_config = {
172 	.multipoint     = 1,
173 	.dyn_fifo       = 1,
174 	.num_eps        = 16,
175 	.ram_bits       = 12,
176 };
177 
178 static struct omap_musb_board_data musb_board_data = {
179 	.interface_type	= MUSB_INTERFACE_ULPI,
180 };
181 
182 static struct musb_hdrc_platform_data musb_plat = {
183 #if defined(CONFIG_USB_MUSB_HOST)
184 	.mode           = MUSB_HOST,
185 #elif defined(CONFIG_USB_MUSB_GADGET)
186 	.mode		= MUSB_PERIPHERAL,
187 #else
188 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
189 #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
190 	.config         = &musb_config,
191 	.power          = 100,
192 	.platform_ops	= &omap2430_ops,
193 	.board_data	= &musb_board_data,
194 };
195 #endif /* CONFIG_USB_MUSB_OMAP2PLUS */
196 
197 /*
198  * Routine: misc_init_r
199  * Description: Init ethernet (done here so udelay works)
200  */
201 int misc_init_r(void)
202 {
203 	twl4030_power_init();
204 
205 #ifdef CONFIG_SYS_I2C_OMAP24XX
206 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
207 #endif
208 
209 #if defined(CONFIG_CMD_NET)
210 	setup_net_chip();
211 #endif
212 	omap3_evm_get_revision();
213 
214 #if defined(CONFIG_CMD_NET)
215 	reset_net_chip();
216 #endif
217 	omap_die_id_display();
218 
219 #if defined(CONFIG_USB_MUSB_OMAP2PLUS)
220 	musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
221 #endif
222 
223 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
224 	omap_die_id_usbethaddr();
225 #endif
226 	return 0;
227 }
228 
229 /*
230  * Routine: set_muxconf_regs
231  * Description: Setting up the configuration Mux registers specific to the
232  *		hardware. Many pins need to be moved from protect to primary
233  *		mode.
234  */
235 void set_muxconf_regs(void)
236 {
237 	MUX_EVM();
238 }
239 
240 #if defined(CONFIG_CMD_NET)
241 /*
242  * Routine: setup_net_chip
243  * Description: Setting up the configuration GPMC registers specific to the
244  *		Ethernet hardware.
245  */
246 static void setup_net_chip(void)
247 {
248 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
249 
250 	/* Configure GPMC registers */
251 	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
252 	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
253 	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
254 	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
255 	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
256 	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
257 	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
258 
259 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
260 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
261 	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
262 	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
263 	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
264 	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
265 		&ctrl_base->gpmc_nadv_ale);
266 }
267 
268 /**
269  * Reset the ethernet chip.
270  */
271 static void reset_net_chip(void)
272 {
273 	int ret;
274 	int rst_gpio;
275 
276 	if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
277 		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
278 	} else {
279 		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
280 	}
281 
282 	ret = gpio_request(rst_gpio, "");
283 	if (ret < 0) {
284 		printf("Unable to get GPIO %d\n", rst_gpio);
285 		return ;
286 	}
287 
288 	/* Configure as output */
289 	gpio_direction_output(rst_gpio, 0);
290 
291 	/* Send a pulse on the GPIO pin */
292 	gpio_set_value(rst_gpio, 1);
293 	udelay(1);
294 	gpio_set_value(rst_gpio, 0);
295 	udelay(1);
296 	gpio_set_value(rst_gpio, 1);
297 }
298 
299 int board_eth_init(bd_t *bis)
300 {
301 #if defined(CONFIG_SMC911X)
302 	env_set("ethaddr", NULL);
303 	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
304 #else
305 	return 0;
306 #endif
307 }
308 #endif /* CONFIG_CMD_NET */
309 
310 #if defined(CONFIG_MMC)
311 int board_mmc_init(bd_t *bis)
312 {
313 	return omap_mmc_init(0, 0, 0, -1, -1);
314 }
315 
316 void board_mmc_power_init(void)
317 {
318 	twl4030_power_mmc_init(0);
319 }
320 #endif /* CONFIG_MMC */
321 
322 #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
323 /* Call usb_stop() before starting the kernel */
324 void show_boot_progress(int val)
325 {
326 	if (val == BOOTSTAGE_ID_RUN_OS)
327 		usb_stop();
328 }
329 
330 static struct omap_usbhs_board_data usbhs_bdata = {
331 	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
332 	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
333 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
334 };
335 
336 int ehci_hcd_init(int index, enum usb_init_type init,
337 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
338 {
339 	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
340 }
341 
342 int ehci_hcd_stop(int index)
343 {
344 	return omap_ehci_hcd_stop();
345 }
346 #endif /* CONFIG_USB_EHCI_HCD */
347 
348 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET)
349 int board_eth_init(bd_t *bis)
350 {
351 	return usb_eth_initialize(bis);
352 }
353 #endif /* CONFIG_USB_ETHER */
354