1 /* 2 * (C) Copyright 2004-2008 3 * Texas Instruments, <www.ti.com> 4 * 5 * Author : 6 * Manikandan Pillai <mani.pillai@ti.com> 7 * 8 * Derived from Beagle Board and 3430 SDP code by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 #include <common.h> 31 #include <netdev.h> 32 #include <asm/io.h> 33 #include <asm/arch/mem.h> 34 #include <asm/arch/mux.h> 35 #include <asm/arch/sys_proto.h> 36 #include <i2c.h> 37 #include <asm/mach-types.h> 38 #include "evm.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 static u32 omap3_evm_version; 43 44 u32 get_omap3_evm_rev(void) 45 { 46 return omap3_evm_version; 47 } 48 49 static void omap3_evm_get_revision(void) 50 { 51 #if defined(CONFIG_CMD_NET) 52 /* 53 * Board revision can be ascertained only by identifying 54 * the Ethernet chipset. 55 */ 56 unsigned int smsc_id; 57 58 /* Ethernet PHY ID is stored at ID_REV register */ 59 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; 60 printf("Read back SMSC id 0x%x\n", smsc_id); 61 62 switch (smsc_id) { 63 /* SMSC9115 chipset */ 64 case 0x01150000: 65 omap3_evm_version = OMAP3EVM_BOARD_GEN_1; 66 break; 67 /* SMSC 9220 chipset */ 68 case 0x92200000: 69 default: 70 omap3_evm_version = OMAP3EVM_BOARD_GEN_2; 71 } 72 #else 73 #if defined(CONFIG_STATIC_BOARD_REV) 74 /* 75 * Look for static defintion of the board revision 76 */ 77 omap3_evm_version = CONFIG_STATIC_BOARD_REV; 78 #else 79 /* 80 * Fallback to the default above. 81 */ 82 omap3_evm_version = OMAP3EVM_BOARD_GEN_2; 83 #endif 84 #endif /* CONFIG_CMD_NET */ 85 } 86 87 #ifdef CONFIG_USB_OMAP3 88 /* 89 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. 90 */ 91 u8 omap3_evm_need_extvbus(void) 92 { 93 u8 retval = 0; 94 95 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 96 retval = 1; 97 98 return retval; 99 } 100 #endif 101 102 /* 103 * Routine: board_init 104 * Description: Early hardware init. 105 */ 106 int board_init(void) 107 { 108 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 109 /* board id for Linux */ 110 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; 111 /* boot param addr */ 112 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 113 114 return 0; 115 } 116 117 /* 118 * Routine: misc_init_r 119 * Description: Init ethernet (done here so udelay works) 120 */ 121 int misc_init_r(void) 122 { 123 124 #ifdef CONFIG_DRIVER_OMAP34XX_I2C 125 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 126 #endif 127 128 #if defined(CONFIG_CMD_NET) 129 setup_net_chip(); 130 #endif 131 omap3_evm_get_revision(); 132 133 dieid_num_r(); 134 135 return 0; 136 } 137 138 /* 139 * Routine: set_muxconf_regs 140 * Description: Setting up the configuration Mux registers specific to the 141 * hardware. Many pins need to be moved from protect to primary 142 * mode. 143 */ 144 void set_muxconf_regs(void) 145 { 146 MUX_EVM(); 147 } 148 149 /* 150 * Routine: setup_net_chip 151 * Description: Setting up the configuration GPMC registers specific to the 152 * Ethernet hardware. 153 */ 154 static void setup_net_chip(void) 155 { 156 struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; 157 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 158 159 /* Configure GPMC registers */ 160 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); 161 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); 162 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); 163 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); 164 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); 165 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); 166 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); 167 168 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 169 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 170 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 171 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 172 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 173 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 174 &ctrl_base->gpmc_nadv_ale); 175 176 /* Make GPIO 64 as output pin */ 177 writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); 178 179 /* Now send a pulse on the GPIO pin */ 180 writel(GPIO0, &gpio3_base->setdataout); 181 udelay(1); 182 writel(GPIO0, &gpio3_base->cleardataout); 183 udelay(1); 184 writel(GPIO0, &gpio3_base->setdataout); 185 } 186 187 int board_eth_init(bd_t *bis) 188 { 189 int rc = 0; 190 #ifdef CONFIG_SMC911X 191 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 192 #endif 193 return rc; 194 } 195