xref: /openbmc/u-boot/board/ti/evm/evm.c (revision 395e2142)
1  /*
2   * (C) Copyright 2004-2011
3   * Texas Instruments, <www.ti.com>
4   *
5   * Author :
6   *	Manikandan Pillai <mani.pillai@ti.com>
7   *
8   * Derived from Beagle Board and 3430 SDP code by
9   *	Richard Woodruff <r-woodruff2@ti.com>
10   *	Syed Mohammed Khasim <khasim@ti.com>
11   *
12   * SPDX-License-Identifier:	GPL-2.0+
13   */
14  #include <common.h>
15  #include <netdev.h>
16  #include <asm/io.h>
17  #include <asm/arch/mem.h>
18  #include <asm/arch/mux.h>
19  #include <asm/arch/sys_proto.h>
20  #include <asm/arch/mmc_host_def.h>
21  #include <asm/gpio.h>
22  #include <i2c.h>
23  #include <twl4030.h>
24  #include <asm/mach-types.h>
25  #include <linux/mtd/nand.h>
26  #include "evm.h"
27  
28  #define OMAP3EVM_GPIO_ETH_RST_GEN1		64
29  #define OMAP3EVM_GPIO_ETH_RST_GEN2		7
30  
31  DECLARE_GLOBAL_DATA_PTR;
32  
33  static u32 omap3_evm_version;
34  
35  u32 get_omap3_evm_rev(void)
36  {
37  	return omap3_evm_version;
38  }
39  
40  static void omap3_evm_get_revision(void)
41  {
42  #if defined(CONFIG_CMD_NET)
43  	/*
44  	 * Board revision can be ascertained only by identifying
45  	 * the Ethernet chipset.
46  	 */
47  	unsigned int smsc_id;
48  
49  	/* Ethernet PHY ID is stored at ID_REV register */
50  	smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
51  	printf("Read back SMSC id 0x%x\n", smsc_id);
52  
53  	switch (smsc_id) {
54  	/* SMSC9115 chipset */
55  	case 0x01150000:
56  		omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
57  		break;
58  	/* SMSC 9220 chipset */
59  	case 0x92200000:
60  	default:
61  		omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
62         }
63  #else
64  #if defined(CONFIG_STATIC_BOARD_REV)
65  	/*
66  	 * Look for static defintion of the board revision
67  	 */
68  	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
69  #else
70  	/*
71  	 * Fallback to the default above.
72  	 */
73  	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
74  #endif
75  #endif	/* CONFIG_CMD_NET */
76  }
77  
78  #ifdef CONFIG_USB_OMAP3
79  /*
80   * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
81   */
82  u8 omap3_evm_need_extvbus(void)
83  {
84  	u8 retval = 0;
85  
86  	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
87  		retval = 1;
88  
89  	return retval;
90  }
91  #endif
92  
93  /*
94   * Routine: board_init
95   * Description: Early hardware init.
96   */
97  int board_init(void)
98  {
99  	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
100  	/* board id for Linux */
101  	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
102  	/* boot param addr */
103  	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
104  
105  	return 0;
106  }
107  
108  #ifdef CONFIG_SPL_BUILD
109  /*
110   * Routine: get_board_mem_timings
111   * Description: If we use SPL then there is no x-loader nor config header
112   * so we have to setup the DDR timings ourself on the first bank.  This
113   * provides the timing values back to the function that configures
114   * the memory.
115   */
116  void get_board_mem_timings(struct board_sdrc_timings *timings)
117  {
118  	int pop_mfr, pop_id;
119  
120  	/*
121  	 * We need to identify what PoP memory is on the board so that
122  	 * we know what timings to use.  To map the ID values please see
123  	 * nand_ids.c
124  	 */
125  	identify_nand_chip(&pop_mfr, &pop_id);
126  
127  	if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
128  		/* 256MB DDR */
129  		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
130  		timings->ctrla = HYNIX_V_ACTIMA_200;
131  		timings->ctrlb = HYNIX_V_ACTIMB_200;
132  	} else {
133  		/* 128MB DDR */
134  		timings->mcfg = MICRON_V_MCFG_165(128 << 20);
135  		timings->ctrla = MICRON_V_ACTIMA_165;
136  		timings->ctrlb = MICRON_V_ACTIMB_165;
137  	}
138  	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
139  	timings->mr = MICRON_V_MR_165;
140  }
141  #endif
142  
143  /*
144   * Routine: misc_init_r
145   * Description: Init ethernet (done here so udelay works)
146   */
147  int misc_init_r(void)
148  {
149  
150  #ifdef CONFIG_SYS_I2C_OMAP34XX
151  	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
152  #endif
153  
154  #if defined(CONFIG_CMD_NET)
155  	setup_net_chip();
156  #endif
157  	omap3_evm_get_revision();
158  
159  #if defined(CONFIG_CMD_NET)
160  	reset_net_chip();
161  #endif
162  	omap_die_id_display();
163  
164  	return 0;
165  }
166  
167  /*
168   * Routine: set_muxconf_regs
169   * Description: Setting up the configuration Mux registers specific to the
170   *		hardware. Many pins need to be moved from protect to primary
171   *		mode.
172   */
173  void set_muxconf_regs(void)
174  {
175  	MUX_EVM();
176  }
177  
178  #ifdef CONFIG_CMD_NET
179  /*
180   * Routine: setup_net_chip
181   * Description: Setting up the configuration GPMC registers specific to the
182   *		Ethernet hardware.
183   */
184  static void setup_net_chip(void)
185  {
186  	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
187  
188  	/* Configure GPMC registers */
189  	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
190  	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
191  	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
192  	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
193  	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
194  	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
195  	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
196  
197  	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
198  	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
199  	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
200  	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
201  	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
202  	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
203  		&ctrl_base->gpmc_nadv_ale);
204  }
205  
206  /**
207   * Reset the ethernet chip.
208   */
209  static void reset_net_chip(void)
210  {
211  	int ret;
212  	int rst_gpio;
213  
214  	if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
215  		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
216  	} else {
217  		rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
218  	}
219  
220  	ret = gpio_request(rst_gpio, "");
221  	if (ret < 0) {
222  		printf("Unable to get GPIO %d\n", rst_gpio);
223  		return ;
224  	}
225  
226  	/* Configure as output */
227  	gpio_direction_output(rst_gpio, 0);
228  
229  	/* Send a pulse on the GPIO pin */
230  	gpio_set_value(rst_gpio, 1);
231  	udelay(1);
232  	gpio_set_value(rst_gpio, 0);
233  	udelay(1);
234  	gpio_set_value(rst_gpio, 1);
235  }
236  
237  int board_eth_init(bd_t *bis)
238  {
239  	int rc = 0;
240  #ifdef CONFIG_SMC911X
241  #define STR_ENV_ETHADDR	"ethaddr"
242  
243  	struct eth_device *dev;
244  	uchar eth_addr[6];
245  
246  	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
247  
248  	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
249  		dev = eth_get_dev_by_index(0);
250  		if (dev) {
251  			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
252  		} else {
253  			printf("omap3evm: Couldn't get eth device\n");
254  			rc = -1;
255  		}
256  	}
257  #endif
258  	return rc;
259  }
260  #endif /* CONFIG_CMD_NET */
261  
262  #if defined(CONFIG_GENERIC_MMC)
263  int board_mmc_init(bd_t *bis)
264  {
265  	return omap_mmc_init(0, 0, 0, -1, -1);
266  }
267  #endif
268  
269  #if defined(CONFIG_GENERIC_MMC)
270  void board_mmc_power_init(void)
271  {
272  	twl4030_power_mmc_init(0);
273  }
274  #endif
275