1 /* 2 * (C) Copyright 2004-2008 3 * Texas Instruments, <www.ti.com> 4 * 5 * Author : 6 * Manikandan Pillai <mani.pillai@ti.com> 7 * 8 * Derived from Beagle Board and 3430 SDP code by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 #include <common.h> 31 #include <netdev.h> 32 #include <asm/io.h> 33 #include <asm/arch/mem.h> 34 #include <asm/arch/mux.h> 35 #include <asm/arch/sys_proto.h> 36 #include <i2c.h> 37 #include <asm/mach-types.h> 38 #include "evm.h" 39 40 static u8 omap3_evm_version; 41 42 u8 get_omap3_evm_rev(void) 43 { 44 return omap3_evm_version; 45 } 46 47 static void omap3_evm_get_revision(void) 48 { 49 unsigned int smsc_id; 50 51 /* Ethernet PHY ID is stored at ID_REV register */ 52 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; 53 printf("Read back SMSC id 0x%x\n", smsc_id); 54 55 switch (smsc_id) { 56 /* SMSC9115 chipset */ 57 case 0x01150000: 58 omap3_evm_version = OMAP3EVM_BOARD_GEN_1; 59 break; 60 /* SMSC 9220 chipset */ 61 case 0x92200000: 62 default: 63 omap3_evm_version = OMAP3EVM_BOARD_GEN_2; 64 } 65 } 66 67 /* 68 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. 69 */ 70 u8 omap3_evm_need_extvbus(void) 71 { 72 u8 retval = 0; 73 74 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 75 retval = 1; 76 77 return retval; 78 } 79 80 /* 81 * Routine: board_init 82 * Description: Early hardware init. 83 */ 84 int board_init(void) 85 { 86 DECLARE_GLOBAL_DATA_PTR; 87 88 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 89 /* board id for Linux */ 90 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM; 91 /* boot param addr */ 92 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 93 94 return 0; 95 } 96 97 /* 98 * Routine: misc_init_r 99 * Description: Init ethernet (done here so udelay works) 100 */ 101 int misc_init_r(void) 102 { 103 104 #ifdef CONFIG_DRIVER_OMAP34XX_I2C 105 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 106 #endif 107 108 #if defined(CONFIG_CMD_NET) 109 setup_net_chip(); 110 #endif 111 112 dieid_num_r(); 113 114 return 0; 115 } 116 117 /* 118 * Routine: set_muxconf_regs 119 * Description: Setting up the configuration Mux registers specific to the 120 * hardware. Many pins need to be moved from protect to primary 121 * mode. 122 */ 123 void set_muxconf_regs(void) 124 { 125 MUX_EVM(); 126 } 127 128 /* 129 * Routine: setup_net_chip 130 * Description: Setting up the configuration GPMC registers specific to the 131 * Ethernet hardware. 132 */ 133 static void setup_net_chip(void) 134 { 135 struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE; 136 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 137 138 /* Configure GPMC registers */ 139 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); 140 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); 141 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); 142 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); 143 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); 144 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); 145 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); 146 147 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 148 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 149 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 150 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 151 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 152 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 153 &ctrl_base->gpmc_nadv_ale); 154 155 /* Make GPIO 64 as output pin */ 156 writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); 157 158 /* Now send a pulse on the GPIO pin */ 159 writel(GPIO0, &gpio3_base->setdataout); 160 udelay(1); 161 writel(GPIO0, &gpio3_base->cleardataout); 162 udelay(1); 163 writel(GPIO0, &gpio3_base->setdataout); 164 165 /* determine omap3evm revision */ 166 omap3_evm_get_revision(); 167 } 168 169 int board_eth_init(bd_t *bis) 170 { 171 int rc = 0; 172 #ifdef CONFIG_SMC911X 173 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 174 #endif 175 return rc; 176 } 177